1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
10 #include <debug_uart.h>
12 #include <env_internal.h>
21 #include <asm/arch/clk.h>
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/arch/psu_init_gpl.h>
25 #include <asm/cache.h>
27 #include <asm/ptrace.h>
28 #include <dm/device.h>
29 #include <dm/uclass.h>
31 #include <dwc3-uboot.h>
33 #include <zynqmp_firmware.h>
35 #include <linux/bitops.h>
36 #include <linux/delay.h>
37 #include <linux/sizes.h>
38 #include "../common/board.h"
40 #include "pm_cfg_obj.h"
42 #define ZYNQMP_VERSION_SIZE 7
43 #define EFUSE_VCU_DIS_MASK 0x100
44 #define EFUSE_VCU_DIS_SHIFT 8
45 #define EFUSE_GPU_DIS_MASK 0x20
46 #define EFUSE_GPU_DIS_SHIFT 5
47 #define IDCODE2_PL_INIT_MASK 0x200
48 #define IDCODE2_PL_INIT_SHIFT 9
50 DECLARE_GLOBAL_DATA_PTR;
52 #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
53 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
56 ZYNQMP_VARIANT_EG = BIT(0U),
57 ZYNQMP_VARIANT_EV = BIT(1U),
58 ZYNQMP_VARIANT_CG = BIT(2U),
59 ZYNQMP_VARIANT_DR = BIT(3U),
66 } zynqmp_devices[] = {
70 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
75 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
80 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
86 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
92 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
97 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
103 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
108 .variants = ZYNQMP_VARIANT_EG,
113 .variants = ZYNQMP_VARIANT_EG,
118 .variants = ZYNQMP_VARIANT_EG,
123 .variants = ZYNQMP_VARIANT_EG,
128 .variants = ZYNQMP_VARIANT_DR,
133 .variants = ZYNQMP_VARIANT_DR,
138 .variants = ZYNQMP_VARIANT_DR,
143 .variants = ZYNQMP_VARIANT_DR,
148 .variants = ZYNQMP_VARIANT_DR,
153 .variants = ZYNQMP_VARIANT_DR,
158 .variants = ZYNQMP_VARIANT_DR,
163 .variants = ZYNQMP_VARIANT_DR,
168 .variants = ZYNQMP_VARIANT_DR,
173 .variants = ZYNQMP_VARIANT_DR,
178 .variants = ZYNQMP_VARIANT_DR,
183 .variants = ZYNQMP_VARIANT_DR,
187 static char *zynqmp_get_silicon_idcode_name(void)
191 char name[ZYNQMP_VERSION_SIZE];
192 u32 ret_payload[PAYLOAD_ARG_CNT];
195 ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
197 debug("%s: Getting chipid failed\n", __func__);
203 * payload[0][31:0] = status of the operation
204 * payload[1]] = IDCODE
205 * payload[2][19:0] = Version
206 * payload[2][28:20] = EXTENDED_IDCODE
207 * payload[2][29] = PL_INIT
210 idcode = ret_payload[1];
211 idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
212 debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode,
215 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
216 if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
220 if (i >= ARRAY_SIZE(zynqmp_devices))
223 /* Add device prefix to the name */
224 ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
225 zynqmp_devices[i].device);
229 if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
230 /* Devices with EV variant might be EG/CG/EV family */
231 if (idcode2 & IDCODE2_PL_INIT_MASK) {
232 u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
233 EFUSE_VCU_DIS_SHIFT) << 1 |
234 ((idcode2 & EFUSE_GPU_DIS_MASK) >>
235 EFUSE_GPU_DIS_SHIFT);
238 * Get family name based on extended idcode values as
239 * determined on UG1087, EXTENDED_IDCODE register
244 strncat(name, "ev", 2);
247 strncat(name, "eg", 2);
250 strncat(name, "cg", 2);
253 /* Do not append family name*/
258 * When PL powered down the VCU Disable efuse cannot be
259 * read. So, ignore the bit and just findout if it is CG
262 strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
265 } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
266 /* Devices with CG variant might be EG or CG family */
267 strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
268 } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
269 strncat(name, "eg", 2);
270 } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
271 strncat(name, "dr", 2);
273 debug("Variant not identified\n");
280 int board_early_init_f(void)
282 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
289 /* Delay is required for clocks to be propagated */
293 #ifdef CONFIG_DEBUG_UART
294 /* Uart debug for sure */
296 puts("Debug uart enabled\n"); /* or printch() */
302 static int multi_boot(void)
306 multiboot = readl(&csu_base->multi_boot);
308 printf("Multiboot:\t%d\n", multiboot);
313 #define PS_SYSMON_ANALOG_BUS_VAL 0x3210
314 #define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914
318 #if defined(CONFIG_ZYNQMP_FIRMWARE)
321 uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
323 panic("PMU Firmware device not found - Enable it");
326 #if defined(CONFIG_SPL_BUILD)
327 /* Check *at build time* if the filename is an non-empty string */
328 if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
329 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
330 zynqmp_pm_cfg_obj_size);
332 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
333 xilinx_read_eeprom();
336 printf("EL Level:\tEL%d\n", current_el());
338 /* Bug in ROM sets wrong value in this register */
339 writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
341 #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
342 zynqmppl.name = zynqmp_get_silicon_idcode_name();
343 printf("Chip ID:\t%s\n", zynqmppl.name);
345 fpga_add(fpga_xilinx, &zynqmppl);
348 if (current_el() == 3)
354 int board_early_init_r(void)
358 if (current_el() != 3)
361 val = readl(&crlapb_base->timestamp_ref_ctrl);
362 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
365 val = readl(&crlapb_base->timestamp_ref_ctrl);
366 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
367 writel(val, &crlapb_base->timestamp_ref_ctrl);
369 /* Program freq register in System counter */
370 writel(zynqmp_get_system_timer_freq(),
371 &iou_scntr_secure->base_frequency_id_register);
372 /* And enable system counter */
373 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
374 &iou_scntr_secure->counter_control_register);
379 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
384 if (current_el() > 1) {
387 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
390 printf("FAIL: current EL is not above EL1\n");
396 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
397 int dram_init_banksize(void)
401 ret = fdtdec_setup_memory_banksize();
412 if (fdtdec_setup_mem_size_base() != 0)
418 int dram_init_banksize(void)
420 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
421 gd->bd->bi_dram[0].size = get_effective_memsize();
430 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
431 CONFIG_SYS_SDRAM_SIZE);
437 void reset_cpu(ulong addr)
441 static u8 __maybe_unused zynqmp_get_bootmode(void)
447 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
451 if (reg >> BOOT_MODE_ALT_SHIFT)
452 reg >>= BOOT_MODE_ALT_SHIFT;
454 bootmode = reg & BOOT_MODES_MASK;
459 #if defined(CONFIG_BOARD_LATE_INIT)
460 static const struct {
463 } reset_reasons[] = {
464 { RESET_REASON_DEBUG_SYS, "DEBUG" },
465 { RESET_REASON_SOFT, "SOFT" },
466 { RESET_REASON_SRST, "SRST" },
467 { RESET_REASON_PSONLY, "PS-ONLY" },
468 { RESET_REASON_PMU, "PMU" },
469 { RESET_REASON_INTERNAL, "INTERNAL" },
470 { RESET_REASON_EXTERNAL, "EXTERNAL" },
474 static int reset_reason(void)
478 const char *reason = NULL;
480 ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®);
484 puts("Reset reason:\t");
486 for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
487 if (reg & reset_reasons[i].bit) {
488 reason = reset_reasons[i].name;
489 printf("%s ", reset_reasons[i].name);
496 env_set("reset_reason", reason);
498 ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
505 static int set_fdtfile(void)
507 char *compatible, *fdtfile;
508 const char *suffix = ".dtb";
509 const char *vendor = "xilinx/";
512 if (env_get("fdtfile"))
515 compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
517 if (compatible && fdt_compat_len) {
520 debug("Compatible: %s\n", compatible);
522 name = strchr(compatible, ',');
528 fdtfile = calloc(1, strlen(vendor) + strlen(name) +
533 sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
535 env_set("fdtfile", fdtfile);
542 int board_late_init(void)
548 int env_targets_len = 0;
554 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
558 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
559 debug("Saved variables - Skipping\n");
563 if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
570 bootmode = zynqmp_get_bootmode();
577 env_set("modeboot", "usb_dfu_spl");
581 mode = "jtag pxe dhcp";
582 env_set("modeboot", "jtagboot");
584 case QSPI_MODE_24BIT:
585 case QSPI_MODE_32BIT:
588 env_set("modeboot", "qspiboot");
592 if (uclass_get_device_by_name(UCLASS_MMC,
593 "mmc@ff160000", &dev) &&
594 uclass_get_device_by_name(UCLASS_MMC,
595 "sdhci@ff160000", &dev)) {
596 puts("Boot from EMMC but without SD0 enabled!\n");
599 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
606 if (uclass_get_device_by_name(UCLASS_MMC,
607 "mmc@ff160000", &dev) &&
608 uclass_get_device_by_name(UCLASS_MMC,
609 "sdhci@ff160000", &dev)) {
610 puts("Boot from SD0 but without SD0 enabled!\n");
613 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
617 env_set("modeboot", "sdboot");
624 if (uclass_get_device_by_name(UCLASS_MMC,
625 "mmc@ff170000", &dev) &&
626 uclass_get_device_by_name(UCLASS_MMC,
627 "sdhci@ff170000", &dev)) {
628 puts("Boot from SD1 but without SD1 enabled!\n");
631 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
635 env_set("modeboot", "sdboot");
640 env_set("modeboot", "nandboot");
644 printf("Invalid Boot Mode:0x%x\n", bootmode);
649 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
650 debug("Bootseq len: %x\n", bootseq_len);
654 * One terminating char + one byte for space between mode
655 * and default boot_targets
657 env_targets = env_get("boot_targets");
659 env_targets_len = strlen(env_targets);
661 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
667 sprintf(new_targets, "%s%x %s", mode, bootseq,
668 env_targets ? env_targets : "");
670 sprintf(new_targets, "%s %s", mode,
671 env_targets ? env_targets : "");
673 env_set("boot_targets", new_targets);
677 return board_late_init_xilinx();
683 puts("Board: Xilinx ZynqMP\n");
687 enum env_location env_get_location(enum env_operation op, int prio)
689 u32 bootmode = zynqmp_get_bootmode();
699 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
701 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
705 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
707 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
710 case QSPI_MODE_24BIT:
711 case QSPI_MODE_32BIT:
712 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
713 return ENVL_SPI_FLASH;