1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/psu_init_gpl.h>
19 #include <dm/device.h>
20 #include <dm/uclass.h>
22 #include <dwc3-uboot.h>
26 #include "pm_cfg_obj.h"
28 DECLARE_GLOBAL_DATA_PTR;
30 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
31 !defined(CONFIG_SPL_BUILD)
32 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
39 } zynqmp_devices[] = {
131 { /* For testing purpose only */
179 int chip_id(unsigned char id)
184 if (current_el() != 3) {
185 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
194 * regs[0][31:0] = status of the operation
195 * regs[0][63:32] = CSU.IDCODE register
196 * regs[1][31:0] = CSU.version register
197 * regs[1][63:32] = CSU.IDCODE2 register
201 regs.regs[0] = upper_32_bits(regs.regs[0]);
202 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
203 ZYNQMP_CSU_IDCODE_SVD_MASK;
204 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
208 regs.regs[1] = lower_32_bits(regs.regs[1]);
209 regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
213 regs.regs[1] = lower_32_bits(regs.regs[1]);
214 regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
218 printf("%s, Invalid Req:0x%x\n", __func__, id);
223 val = readl(ZYNQMP_CSU_IDCODE_ADDR);
224 val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
225 ZYNQMP_CSU_IDCODE_SVD_MASK;
226 val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
229 val = readl(ZYNQMP_CSU_VER_ADDR);
230 val &= ZYNQMP_CSU_SILICON_VER_MASK;
233 printf("%s, Invalid Req:0x%x\n", __func__, id);
240 #define ZYNQMP_VERSION_SIZE 9
241 #define ZYNQMP_PL_STATUS_BIT 9
242 #define ZYNQMP_IPDIS_VCU_BIT 8
243 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
244 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
245 #define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \
246 ~BIT(ZYNQMP_IPDIS_VCU_BIT)
247 #define MAX_VARIANTS_EV 3
249 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
250 !defined(CONFIG_SPL_BUILD)
251 static char *zynqmp_get_silicon_idcode_name(void)
255 static char name[ZYNQMP_VERSION_SIZE];
257 id = chip_id(IDCODE);
258 ver = chip_id(IDCODE2);
260 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
261 if (zynqmp_devices[i].id == id) {
262 if (zynqmp_devices[i].evexists &&
263 !(ver & ZYNQMP_PL_STATUS_MASK))
265 if (zynqmp_devices[i].ver == (ver &
266 ZYNQMP_CSU_VERSION_MASK))
271 if (i >= ARRAY_SIZE(zynqmp_devices))
274 strncat(name, "zu", 2);
275 if (!zynqmp_devices[i].evexists ||
276 (ver & ZYNQMP_PL_STATUS_MASK)) {
277 strncat(name, zynqmp_devices[i].name,
278 ZYNQMP_VERSION_SIZE - 3);
283 * Here we are means, PL not powered up and ev variant
284 * exists. So, we need to ignore VCU disable bit(8) in
285 * version and findout if its CG or EG/EV variant.
287 for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
288 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
289 (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
290 strncat(name, zynqmp_devices[i].name,
291 ZYNQMP_VERSION_SIZE - 3);
296 if (j >= MAX_VARIANTS_EV)
299 if (strstr(name, "eg") || strstr(name, "ev")) {
300 buf = strstr(name, "e");
308 int board_early_init_f(void)
311 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
314 pm_api_version = zynqmp_pmufw_version();
315 printf("PMUFW:\tv%d.%d\n",
316 pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
317 pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
319 if (pm_api_version < ZYNQMP_PM_VERSION)
320 panic("PMUFW version error. Expected: v%d.%d\n",
321 ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
324 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
333 #if defined(CONFIG_SPL_BUILD)
334 /* Check *at build time* if the filename is an non-empty string */
335 if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
336 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
337 zynqmp_pm_cfg_obj_size);
340 printf("EL Level:\tEL%d\n", current_el());
342 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
343 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
344 defined(CONFIG_SPL_BUILD))
345 if (current_el() != 3) {
346 zynqmppl.name = zynqmp_get_silicon_idcode_name();
347 printf("Chip ID:\t%s\n", zynqmppl.name);
349 fpga_add(fpga_xilinx, &zynqmppl);
356 int board_early_init_r(void)
360 if (current_el() != 3)
363 val = readl(&crlapb_base->timestamp_ref_ctrl);
364 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
367 val = readl(&crlapb_base->timestamp_ref_ctrl);
368 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
369 writel(val, &crlapb_base->timestamp_ref_ctrl);
371 /* Program freq register in System counter */
372 writel(zynqmp_get_system_timer_freq(),
373 &iou_scntr_secure->base_frequency_id_register);
374 /* And enable system counter */
375 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
376 &iou_scntr_secure->counter_control_register);
381 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
386 if (current_el() > 1) {
389 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
392 printf("FAIL: current EL is not above EL1\n");
398 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
399 int dram_init_banksize(void)
403 ret = fdtdec_setup_memory_banksize();
414 if (fdtdec_setup_mem_size_base() != 0)
420 int dram_init_banksize(void)
422 #if defined(CONFIG_NR_DRAM_BANKS)
423 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
424 gd->bd->bi_dram[0].size = get_effective_memsize();
434 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
435 CONFIG_SYS_SDRAM_SIZE);
441 void reset_cpu(ulong addr)
445 #if defined(CONFIG_BOARD_LATE_INIT)
446 static const struct {
449 } reset_reasons[] = {
450 { RESET_REASON_DEBUG_SYS, "DEBUG" },
451 { RESET_REASON_SOFT, "SOFT" },
452 { RESET_REASON_SRST, "SRST" },
453 { RESET_REASON_PSONLY, "PS-ONLY" },
454 { RESET_REASON_PMU, "PMU" },
455 { RESET_REASON_INTERNAL, "INTERNAL" },
456 { RESET_REASON_EXTERNAL, "EXTERNAL" },
460 static int reset_reason(void)
464 const char *reason = NULL;
466 ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®);
470 puts("Reset reason:\t");
472 for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
473 if (reg & reset_reasons[i].bit) {
474 reason = reset_reasons[i].name;
475 printf("%s ", reset_reasons[i].name);
482 env_set("reset_reason", reason);
484 ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
491 static int set_fdtfile(void)
493 char *compatible, *fdtfile;
494 const char *suffix = ".dtb";
495 const char *vendor = "xilinx/";
497 if (env_get("fdtfile"))
500 compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
502 debug("Compatible: %s\n", compatible);
504 /* Discard vendor prefix */
505 strsep(&compatible, ",");
507 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
512 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
514 env_set("fdtfile", fdtfile);
521 int board_late_init(void)
528 int env_targets_len = 0;
534 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
538 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
539 debug("Saved variables - Skipping\n");
547 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
551 if (reg >> BOOT_MODE_ALT_SHIFT)
552 reg >>= BOOT_MODE_ALT_SHIFT;
554 bootmode = reg & BOOT_MODES_MASK;
561 env_set("modeboot", "usb_dfu_spl");
566 env_set("modeboot", "jtagboot");
568 case QSPI_MODE_24BIT:
569 case QSPI_MODE_32BIT:
572 env_set("modeboot", "qspiboot");
577 env_set("modeboot", "emmcboot");
581 if (uclass_get_device_by_name(UCLASS_MMC,
582 "mmc@ff160000", &dev) &&
583 uclass_get_device_by_name(UCLASS_MMC,
584 "sdhci@ff160000", &dev)) {
585 puts("Boot from SD0 but without SD0 enabled!\n");
588 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
592 env_set("modeboot", "sdboot");
599 if (uclass_get_device_by_name(UCLASS_MMC,
600 "mmc@ff170000", &dev) &&
601 uclass_get_device_by_name(UCLASS_MMC,
602 "sdhci@ff170000", &dev)) {
603 puts("Boot from SD1 but without SD1 enabled!\n");
606 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
610 env_set("modeboot", "sdboot");
615 env_set("modeboot", "nandboot");
619 printf("Invalid Boot Mode:0x%x\n", bootmode);
624 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
625 debug("Bootseq len: %x\n", bootseq_len);
629 * One terminating char + one byte for space between mode
630 * and default boot_targets
632 env_targets = env_get("boot_targets");
634 env_targets_len = strlen(env_targets);
636 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
642 sprintf(new_targets, "%s%x %s", mode, bootseq,
643 env_targets ? env_targets : "");
645 sprintf(new_targets, "%s %s", mode,
646 env_targets ? env_targets : "");
648 env_set("boot_targets", new_targets);
658 puts("Board: Xilinx ZynqMP\n");