2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
18 #include <dwc3-uboot.h>
20 DECLARE_GLOBAL_DATA_PTR;
24 printf("EL Level:\tEL%d\n", current_el());
29 int board_early_init_r(void)
33 if (current_el() == 3) {
34 val = readl(&crlapb_base->timestamp_ref_ctrl);
35 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
36 writel(val, &crlapb_base->timestamp_ref_ctrl);
38 /* Program freq register in System counter */
39 writel(zynqmp_get_system_timer_freq(),
40 &iou_scntr_secure->base_frequency_id_register);
41 /* And enable system counter */
42 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
43 &iou_scntr_secure->counter_control_register);
45 /* Program freq register in System counter and enable system counter */
46 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
47 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
48 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
49 &iou_scntr->counter_control_register);
54 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
56 * fdt_get_reg - Fill buffer by information from DT
58 static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
59 const u32 *cell, int n)
62 int parent_offset = fdt_parent_offset(fdt, nodeoffset);
63 int address_cells = fdt_address_cells(fdt, parent_offset);
64 int size_cells = fdt_size_cells(fdt, parent_offset);
69 debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
70 __func__, address_cells, size_cells, buf, cell);
72 /* Check memory bank setup */
73 banks = n % (address_cells + size_cells);
75 panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
76 n, address_cells, size_cells);
78 banks = n / (address_cells + size_cells);
80 for (b = 0; b < banks; b++) {
81 debug("%s: Bank #%d:\n", __func__, b);
82 if (address_cells == 2) {
86 val = fdt64_to_cpu(val);
87 debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
88 __func__, val, p, &cell[i]);
89 *(phys_addr_t *)p = val;
91 debug("%s: addr32=%x, ptr=%p\n",
92 __func__, fdt32_to_cpu(cell[i]), p);
93 *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
95 p += sizeof(phys_addr_t);
98 debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
101 if (size_cells == 2) {
105 vals = fdt64_to_cpu(vals);
107 debug("%s: size64=%llx, ptr=%p, cell=%p\n",
108 __func__, vals, p, &cell[i]);
109 *(phys_size_t *)p = vals;
111 debug("%s: size32=%x, ptr=%p\n",
112 __func__, fdt32_to_cpu(cell[i]), p);
113 *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
115 p += sizeof(phys_size_t);
118 debug("%s: ps=%p, i=%x, size=%zu\n",
119 __func__, p, i, sizeof(phys_size_t));
122 /* Return the first address size */
123 return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
126 #define FDT_REG_SIZE sizeof(u32)
127 /* Temp location for sharing data for storing */
128 /* Up to 64-bit address + 64-bit size */
129 static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
131 void dram_init_banksize(void)
135 memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
137 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
138 debug("Bank #%d: start %llx\n", bank,
139 (unsigned long long)gd->bd->bi_dram[bank].start);
140 debug("Bank #%d: size %llx\n", bank,
141 (unsigned long long)gd->bd->bi_dram[bank].size);
148 const void *blob = gd->fdt_blob;
151 memset(&tmp, 0, sizeof(tmp));
153 /* find or create "/memory" node. */
154 node = fdt_subnode_offset(blob, 0, "memory");
156 printf("%s: Can't get memory node\n", __func__);
160 /* Get pointer to cells and lenght of it */
161 cell = fdt_getprop(blob, node, "reg", &len);
163 printf("%s: Can't get reg property\n", __func__);
167 gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
169 debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size);
176 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
182 void reset_cpu(ulong addr)
186 #ifdef CONFIG_SCSI_AHCI_PLAT
189 #if defined(CONFIG_SATA_CEVA)
192 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
197 int board_late_init(void)
202 reg = readl(&crlapb_base->boot_mode);
203 bootmode = reg & BOOT_MODES_MASK;
209 setenv("modeboot", "jtagboot");
211 case QSPI_MODE_24BIT:
212 case QSPI_MODE_32BIT:
213 setenv("modeboot", "qspiboot");
218 setenv("modeboot", "sdboot");
222 setenv("modeboot", "sdboot");
226 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
227 setenv("sdbootdev", "1");
229 setenv("modeboot", "sdboot");
233 setenv("modeboot", "nandboot");
236 printf("Invalid Boot Mode:0x%x\n", bootmode);
245 puts("Board: Xilinx ZynqMP\n");
249 #ifdef CONFIG_USB_DWC3
250 static struct dwc3_device dwc3_device_data = {
251 .maximum_speed = USB_SPEED_HIGH,
252 .base = ZYNQMP_USB0_XHCI_BASEADDR,
253 .dr_mode = USB_DR_MODE_PERIPHERAL,
257 int usb_gadget_handle_interrupts(void)
259 dwc3_uboot_handle_interrupt(0);
263 int board_usb_init(int index, enum usb_init_type init)
265 return dwc3_uboot_init(&dwc3_device_data);
268 int board_usb_cleanup(int index, enum usb_init_type init)
270 dwc3_uboot_exit(index);