board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cpu_func.h>
  10 #include <debug_uart.h>
  11 #include <env.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <net.h>
  15 #include <sata.h>
  16 #include <ahci.h>
  17 #include <scsi.h>
  18 #include <malloc.h>
  19 #include <wdt.h>
  20 #include <asm/arch/clk.h>
  21 #include <asm/arch/hardware.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/psu_init_gpl.h>
  24 #include <asm/cache.h>
  25 #include <asm/io.h>
  26 #include <asm/ptrace.h>
  27 #include <dm/device.h>
  28 #include <dm/uclass.h>
  29 #include <usb.h>
  30 #include <dwc3-uboot.h>
  31 #include <zynqmppl.h>
  32 #include <zynqmp_firmware.h>
  33 #include <g_dnl.h>
  34 #include <linux/bitops.h>
  35 #include <linux/delay.h>
  36 #include <linux/sizes.h>
  37 #include "../common/board.h"
  38
  39 #include "pm_cfg_obj.h"
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  44     !defined(CONFIG_SPL_BUILD)
  45 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  46
  47 static const struct {
  48         u32 id;
  49         u32 ver;
  50         char *name;
  51         bool evexists;
  52 } zynqmp_devices[] = {
  53         {
  54                 .id = 0x10,
  55                 .name = "3eg",
  56         },
  57         {
  58                 .id = 0x10,
  59                 .ver = 0x2c,
  60                 .name = "3cg",
  61         },
  62         {
  63                 .id = 0x11,
  64                 .name = "2eg",
  65         },
  66         {
  67                 .id = 0x11,
  68                 .ver = 0x2c,
  69                 .name = "2cg",
  70         },
  71         {
  72                 .id = 0x20,
  73                 .name = "5ev",
  74                 .evexists = 1,
  75         },
  76         {
  77                 .id = 0x20,
  78                 .ver = 0x100,
  79                 .name = "5eg",
  80                 .evexists = 1,
  81         },
  82         {
  83                 .id = 0x20,
  84                 .ver = 0x12c,
  85                 .name = "5cg",
  86                 .evexists = 1,
  87         },
  88         {
  89                 .id = 0x21,
  90                 .name = "4ev",
  91                 .evexists = 1,
  92         },
  93         {
  94                 .id = 0x21,
  95                 .ver = 0x100,
  96                 .name = "4eg",
  97                 .evexists = 1,
  98         },
  99         {
 100                 .id = 0x21,
 101                 .ver = 0x12c,
 102                 .name = "4cg",
 103                 .evexists = 1,
 104         },
 105         {
 106                 .id = 0x30,
 107                 .name = "7ev",
 108                 .evexists = 1,
 109         },
 110         {
 111                 .id = 0x30,
 112                 .ver = 0x100,
 113                 .name = "7eg",
 114                 .evexists = 1,
 115         },
 116         {
 117                 .id = 0x30,
 118                 .ver = 0x12c,
 119                 .name = "7cg",
 120                 .evexists = 1,
 121         },
 122         {
 123                 .id = 0x38,
 124                 .name = "9eg",
 125         },
 126         {
 127                 .id = 0x38,
 128                 .ver = 0x2c,
 129                 .name = "9cg",
 130         },
 131         {
 132                 .id = 0x39,
 133                 .name = "6eg",
 134         },
 135         {
 136                 .id = 0x39,
 137                 .ver = 0x2c,
 138                 .name = "6cg",
 139         },
 140         {
 141                 .id = 0x40,
 142                 .name = "11eg",
 143         },
 144         { /* For testing purpose only */
 145                 .id = 0x50,
 146                 .ver = 0x2c,
 147                 .name = "15cg",
 148         },
 149         {
 150                 .id = 0x50,
 151                 .name = "15eg",
 152         },
 153         {
 154                 .id = 0x58,
 155                 .name = "19eg",
 156         },
 157         {
 158                 .id = 0x59,
 159                 .name = "17eg",
 160         },
 161         {
 162                 .id = 0x61,
 163                 .name = "21dr",
 164         },
 165         {
 166                 .id = 0x63,
 167                 .name = "23dr",
 168         },
 169         {
 170                 .id = 0x65,
 171                 .name = "25dr",
 172         },
 173         {
 174                 .id = 0x64,
 175                 .name = "27dr",
 176         },
 177         {
 178                 .id = 0x60,
 179                 .name = "28dr",
 180         },
 181         {
 182                 .id = 0x62,
 183                 .name = "29dr",
 184         },
 185         {
 186                 .id = 0x66,
 187                 .name = "39dr",
 188         },
 189         {
 190                 .id = 0x7b,
 191                 .name = "48dr",
 192         },
 193         {
 194                 .id = 0x7e,
 195                 .name = "49dr",
 196         },
 197 };
 198 #endif
 199
 200 int chip_id(unsigned char id)
 201 {
 202         struct pt_regs regs;
 203         int val = -EINVAL;
 204
 205         if (current_el() != 3) {
 206                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 207                 regs.regs[1] = 0;
 208                 regs.regs[2] = 0;
 209                 regs.regs[3] = 0;
 210
 211                 smc_call(&regs);
 212
 213                 /*
 214                  * SMC returns:
 215                  * regs[0][31:0]  = status of the operation
 216                  * regs[0][63:32] = CSU.IDCODE register
 217                  * regs[1][31:0]  = CSU.version register
 218                  * regs[1][63:32] = CSU.IDCODE2 register
 219                  */
 220                 switch (id) {
 221                 case IDCODE:
 222                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 223                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 224                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 225                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 226                         val = regs.regs[0];
 227                         break;
 228                 case VERSION:
 229                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 230                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 231                         val = regs.regs[1];
 232                         break;
 233                 case IDCODE2:
 234                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 235                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 236                         val = regs.regs[1];
 237                         break;
 238                 default:
 239                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 240                 }
 241         } else {
 242                 switch (id) {
 243                 case IDCODE:
 244                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 245                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 246                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 247                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 248                         break;
 249                 case VERSION:
 250                         val = readl(ZYNQMP_CSU_VER_ADDR);
 251                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 252                         break;
 253                 default:
 254                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 255                 }
 256         }
 257
 258         return val;
 259 }
 260
 261 #define ZYNQMP_VERSION_SIZE             9
 262 #define ZYNQMP_PL_STATUS_BIT            9
 263 #define ZYNQMP_IPDIS_VCU_BIT            8
 264 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 265 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 266 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 267                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 268 #define MAX_VARIANTS_EV                 3
 269
 270 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 271         !defined(CONFIG_SPL_BUILD)
 272 static char *zynqmp_get_silicon_idcode_name(void)
 273 {
 274         u32 i, id, ver, j;
 275         char *buf;
 276         static char name[ZYNQMP_VERSION_SIZE];
 277
 278         id = chip_id(IDCODE);
 279         ver = chip_id(IDCODE2);
 280
 281         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 282                 if (zynqmp_devices[i].id == id) {
 283                         if (zynqmp_devices[i].evexists &&
 284                             !(ver & ZYNQMP_PL_STATUS_MASK))
 285                                 break;
 286                         if (zynqmp_devices[i].ver == (ver &
 287                             ZYNQMP_CSU_VERSION_MASK))
 288                                 break;
 289                 }
 290         }
 291
 292         if (i >= ARRAY_SIZE(zynqmp_devices))
 293                 return "unknown";
 294
 295         strncat(name, "zu", 2);
 296         if (!zynqmp_devices[i].evexists ||
 297             (ver & ZYNQMP_PL_STATUS_MASK)) {
 298                 strncat(name, zynqmp_devices[i].name,
 299                         ZYNQMP_VERSION_SIZE - 3);
 300                 return name;
 301         }
 302
 303         /*
 304          * Here we are means, PL not powered up and ev variant
 305          * exists. So, we need to ignore VCU disable bit(8) in
 306          * version and findout if its CG or EG/EV variant.
 307          */
 308         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 309                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 310                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 311                         strncat(name, zynqmp_devices[i].name,
 312                                 ZYNQMP_VERSION_SIZE - 3);
 313                         break;
 314                 }
 315         }
 316
 317         if (j >= MAX_VARIANTS_EV)
 318                 return "unknown";
 319
 320         if (strstr(name, "eg") || strstr(name, "ev")) {
 321                 buf = strstr(name, "e");
 322                 *buf = '\0';
 323         }
 324
 325         return name;
 326 }
 327 #endif
 328
 329 int board_early_init_f(void)
 330 {
 331 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 332         int ret;
 333
 334         ret = psu_init();
 335         if (ret)
 336                 return ret;
 337
 338         /* Delay is required for clocks to be propagated */
 339         udelay(1000000);
 340 #endif
 341
 342 #ifdef CONFIG_DEBUG_UART
 343         /* Uart debug for sure */
 344         debug_uart_init();
 345         puts("Debug uart enabled\n"); /* or printch() */
 346 #endif
 347
 348         return 0;
 349 }
 350
 351 static int multi_boot(void)
 352 {
 353         u32 multiboot;
 354
 355         multiboot = readl(&csu_base->multi_boot);
 356
 357         printf("Multiboot:\t%x\n", multiboot);
 358
 359         return 0;
 360 }
 361
 362 int board_init(void)
 363 {
 364 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 365         struct udevice *dev;
 366
 367         uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
 368         if (!dev)
 369                 panic("PMU Firmware device not found - Enable it");
 370 #endif
 371
 372 #if defined(CONFIG_SPL_BUILD)
 373         /* Check *at build time* if the filename is an non-empty string */
 374         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 375                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 376                                                 zynqmp_pm_cfg_obj_size);
 377 #endif
 378
 379         printf("EL Level:\tEL%d\n", current_el());
 380
 381 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 382     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 383     defined(CONFIG_SPL_BUILD))
 384         if (current_el() != 3) {
 385                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 386                 printf("Chip ID:\t%s\n", zynqmppl.name);
 387                 fpga_init();
 388                 fpga_add(fpga_xilinx, &zynqmppl);
 389         }
 390 #endif
 391
 392         if (current_el() == 3)
 393                 multi_boot();
 394
 395         return 0;
 396 }
 397
 398 int board_early_init_r(void)
 399 {
 400         u32 val;
 401
 402         if (current_el() != 3)
 403                 return 0;
 404
 405         val = readl(&crlapb_base->timestamp_ref_ctrl);
 406         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 407
 408         if (!val) {
 409                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 410                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 411                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 412
 413                 /* Program freq register in System counter */
 414                 writel(zynqmp_get_system_timer_freq(),
 415                        &iou_scntr_secure->base_frequency_id_register);
 416                 /* And enable system counter */
 417                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 418                        &iou_scntr_secure->counter_control_register);
 419         }
 420         return 0;
 421 }
 422
 423 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 424                          char *const argv[])
 425 {
 426         int ret = 0;
 427
 428         if (current_el() > 1) {
 429                 smp_kick_all_cpus();
 430                 dcache_disable();
 431                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 432                                     ES_TO_AARCH64);
 433         } else {
 434                 printf("FAIL: current EL is not above EL1\n");
 435                 ret = EINVAL;
 436         }
 437         return ret;
 438 }
 439
 440 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 441 int dram_init_banksize(void)
 442 {
 443         int ret;
 444
 445         ret = fdtdec_setup_memory_banksize();
 446         if (ret)
 447                 return ret;
 448
 449         mem_map_fill();
 450
 451         return 0;
 452 }
 453
 454 int dram_init(void)
 455 {
 456         if (fdtdec_setup_mem_size_base() != 0)
 457                 return -EINVAL;
 458
 459         return 0;
 460 }
 461 #else
 462 int dram_init_banksize(void)
 463 {
 464 #if defined(CONFIG_NR_DRAM_BANKS)
 465         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 466         gd->bd->bi_dram[0].size = get_effective_memsize();
 467 #endif
 468
 469         mem_map_fill();
 470
 471         return 0;
 472 }
 473
 474 int dram_init(void)
 475 {
 476         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 477                                     CONFIG_SYS_SDRAM_SIZE);
 478
 479         return 0;
 480 }
 481 #endif
 482
 483 void reset_cpu(ulong addr)
 484 {
 485 }
 486
 487 #if defined(CONFIG_BOARD_LATE_INIT)
 488 static const struct {
 489         u32 bit;
 490         const char *name;
 491 } reset_reasons[] = {
 492         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 493         { RESET_REASON_SOFT, "SOFT" },
 494         { RESET_REASON_SRST, "SRST" },
 495         { RESET_REASON_PSONLY, "PS-ONLY" },
 496         { RESET_REASON_PMU, "PMU" },
 497         { RESET_REASON_INTERNAL, "INTERNAL" },
 498         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 499         {}
 500 };
 501
 502 static int reset_reason(void)
 503 {
 504         u32 reg;
 505         int i, ret;
 506         const char *reason = NULL;
 507
 508         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 509         if (ret)
 510                 return -EINVAL;
 511
 512         puts("Reset reason:\t");
 513
 514         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 515                 if (reg & reset_reasons[i].bit) {
 516                         reason = reset_reasons[i].name;
 517                         printf("%s ", reset_reasons[i].name);
 518                         break;
 519                 }
 520         }
 521
 522         puts("\n");
 523
 524         env_set("reset_reason", reason);
 525
 526         ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
 527         if (ret)
 528                 return -EINVAL;
 529
 530         return ret;
 531 }
 532
 533 static int set_fdtfile(void)
 534 {
 535         char *compatible, *fdtfile;
 536         const char *suffix = ".dtb";
 537         const char *vendor = "xilinx/";
 538
 539         if (env_get("fdtfile"))
 540                 return 0;
 541
 542         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 543         if (compatible) {
 544                 debug("Compatible: %s\n", compatible);
 545
 546                 /* Discard vendor prefix */
 547                 strsep(&compatible, ",");
 548
 549                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 550                                  strlen(suffix) + 1);
 551                 if (!fdtfile)
 552                         return -ENOMEM;
 553
 554                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 555
 556                 env_set("fdtfile", fdtfile);
 557                 free(fdtfile);
 558         }
 559
 560         return 0;
 561 }
 562
 563 static u8 zynqmp_get_bootmode(void)
 564 {
 565         u8 bootmode;
 566         u32 reg = 0;
 567         int ret;
 568
 569         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 570         if (ret)
 571                 return -EINVAL;
 572
 573         if (reg >> BOOT_MODE_ALT_SHIFT)
 574                 reg >>= BOOT_MODE_ALT_SHIFT;
 575
 576         bootmode = reg & BOOT_MODES_MASK;
 577
 578         return bootmode;
 579 }
 580
 581 int board_late_init(void)
 582 {
 583         u8 bootmode;
 584         struct udevice *dev;
 585         int bootseq = -1;
 586         int bootseq_len = 0;
 587         int env_targets_len = 0;
 588         const char *mode;
 589         char *new_targets;
 590         char *env_targets;
 591         int ret;
 592
 593 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 594         usb_ether_init();
 595 #endif
 596
 597         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 598                 debug("Saved variables - Skipping\n");
 599                 return 0;
 600         }
 601
 602         ret = set_fdtfile();
 603         if (ret)
 604                 return ret;
 605
 606         bootmode = zynqmp_get_bootmode();
 607
 608         puts("Bootmode: ");
 609         switch (bootmode) {
 610         case USB_MODE:
 611                 puts("USB_MODE\n");
 612                 mode = "usb";
 613                 env_set("modeboot", "usb_dfu_spl");
 614                 break;
 615         case JTAG_MODE:
 616                 puts("JTAG_MODE\n");
 617                 mode = "jtag pxe dhcp";
 618                 env_set("modeboot", "jtagboot");
 619                 break;
 620         case QSPI_MODE_24BIT:
 621         case QSPI_MODE_32BIT:
 622                 mode = "qspi0";
 623                 puts("QSPI_MODE\n");
 624                 env_set("modeboot", "qspiboot");
 625                 break;
 626         case EMMC_MODE:
 627                 puts("EMMC_MODE\n");
 628                 if (uclass_get_device_by_name(UCLASS_MMC,
 629                                               "mmc@ff160000", &dev) &&
 630                     uclass_get_device_by_name(UCLASS_MMC,
 631                                               "sdhci@ff160000", &dev)) {
 632                         puts("Boot from EMMC but without SD0 enabled!\n");
 633                         return -1;
 634                 }
 635                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 636
 637                 mode = "mmc";
 638                 bootseq = dev->seq;
 639                 break;
 640         case SD_MODE:
 641                 puts("SD_MODE\n");
 642                 if (uclass_get_device_by_name(UCLASS_MMC,
 643                                               "mmc@ff160000", &dev) &&
 644                     uclass_get_device_by_name(UCLASS_MMC,
 645                                               "sdhci@ff160000", &dev)) {
 646                         puts("Boot from SD0 but without SD0 enabled!\n");
 647                         return -1;
 648                 }
 649                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 650
 651                 mode = "mmc";
 652                 bootseq = dev->seq;
 653                 env_set("modeboot", "sdboot");
 654                 break;
 655         case SD1_LSHFT_MODE:
 656                 puts("LVL_SHFT_");
 657                 /* fall through */
 658         case SD_MODE1:
 659                 puts("SD_MODE1\n");
 660                 if (uclass_get_device_by_name(UCLASS_MMC,
 661                                               "mmc@ff170000", &dev) &&
 662                     uclass_get_device_by_name(UCLASS_MMC,
 663                                               "sdhci@ff170000", &dev)) {
 664                         puts("Boot from SD1 but without SD1 enabled!\n");
 665                         return -1;
 666                 }
 667                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 668
 669                 mode = "mmc";
 670                 bootseq = dev->seq;
 671                 env_set("modeboot", "sdboot");
 672                 break;
 673         case NAND_MODE:
 674                 puts("NAND_MODE\n");
 675                 mode = "nand0";
 676                 env_set("modeboot", "nandboot");
 677                 break;
 678         default:
 679                 mode = "";
 680                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 681                 break;
 682         }
 683
 684         if (bootseq >= 0) {
 685                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 686                 debug("Bootseq len: %x\n", bootseq_len);
 687         }
 688
 689         /*
 690          * One terminating char + one byte for space between mode
 691          * and default boot_targets
 692          */
 693         env_targets = env_get("boot_targets");
 694         if (env_targets)
 695                 env_targets_len = strlen(env_targets);
 696
 697         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 698                              bootseq_len);
 699         if (!new_targets)
 700                 return -ENOMEM;
 701
 702         if (bootseq >= 0)
 703                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 704                         env_targets ? env_targets : "");
 705         else
 706                 sprintf(new_targets, "%s %s", mode,
 707                         env_targets ? env_targets : "");
 708
 709         env_set("boot_targets", new_targets);
 710
 711         reset_reason();
 712
 713         return board_late_init_xilinx();
 714 }
 715 #endif
 716
 717 int checkboard(void)
 718 {
 719         puts("Board: Xilinx ZynqMP\n");
 720         return 0;
 721 }