board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cpu_func.h>
  10 #include <debug_uart.h>
  11 #include <env.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <net.h>
  15 #include <sata.h>
  16 #include <ahci.h>
  17 #include <scsi.h>
  18 #include <malloc.h>
  19 #include <wdt.h>
  20 #include <asm/arch/clk.h>
  21 #include <asm/arch/hardware.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/psu_init_gpl.h>
  24 #include <asm/cache.h>
  25 #include <asm/io.h>
  26 #include <asm/ptrace.h>
  27 #include <dm/device.h>
  28 #include <dm/uclass.h>
  29 #include <usb.h>
  30 #include <dwc3-uboot.h>
  31 #include <zynqmppl.h>
  32 #include <zynqmp_firmware.h>
  33 #include <g_dnl.h>
  34 #include <linux/bitops.h>
  35 #include <linux/delay.h>
  36 #include <linux/sizes.h>
  37 #include "../common/board.h"
  38
  39 #include "pm_cfg_obj.h"
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  44     !defined(CONFIG_SPL_BUILD)
  45 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  46
  47 static const struct {
  48         u32 id;
  49         u32 ver;
  50         char *name;
  51         bool evexists;
  52 } zynqmp_devices[] = {
  53         {
  54                 .id = 0x10,
  55                 .name = "3eg",
  56         },
  57         {
  58                 .id = 0x10,
  59                 .ver = 0x2c,
  60                 .name = "3cg",
  61         },
  62         {
  63                 .id = 0x11,
  64                 .name = "2eg",
  65         },
  66         {
  67                 .id = 0x11,
  68                 .ver = 0x2c,
  69                 .name = "2cg",
  70         },
  71         {
  72                 .id = 0x20,
  73                 .name = "5ev",
  74                 .evexists = 1,
  75         },
  76         {
  77                 .id = 0x20,
  78                 .ver = 0x100,
  79                 .name = "5eg",
  80                 .evexists = 1,
  81         },
  82         {
  83                 .id = 0x20,
  84                 .ver = 0x12c,
  85                 .name = "5cg",
  86                 .evexists = 1,
  87         },
  88         {
  89                 .id = 0x21,
  90                 .name = "4ev",
  91                 .evexists = 1,
  92         },
  93         {
  94                 .id = 0x21,
  95                 .ver = 0x100,
  96                 .name = "4eg",
  97                 .evexists = 1,
  98         },
  99         {
 100                 .id = 0x21,
 101                 .ver = 0x12c,
 102                 .name = "4cg",
 103                 .evexists = 1,
 104         },
 105         {
 106                 .id = 0x30,
 107                 .name = "7ev",
 108                 .evexists = 1,
 109         },
 110         {
 111                 .id = 0x30,
 112                 .ver = 0x100,
 113                 .name = "7eg",
 114                 .evexists = 1,
 115         },
 116         {
 117                 .id = 0x30,
 118                 .ver = 0x12c,
 119                 .name = "7cg",
 120                 .evexists = 1,
 121         },
 122         {
 123                 .id = 0x38,
 124                 .name = "9eg",
 125         },
 126         {
 127                 .id = 0x38,
 128                 .ver = 0x2c,
 129                 .name = "9cg",
 130         },
 131         {
 132                 .id = 0x39,
 133                 .name = "6eg",
 134         },
 135         {
 136                 .id = 0x39,
 137                 .ver = 0x2c,
 138                 .name = "6cg",
 139         },
 140         {
 141                 .id = 0x40,
 142                 .name = "11eg",
 143         },
 144         { /* For testing purpose only */
 145                 .id = 0x50,
 146                 .ver = 0x2c,
 147                 .name = "15cg",
 148         },
 149         {
 150                 .id = 0x50,
 151                 .name = "15eg",
 152         },
 153         {
 154                 .id = 0x58,
 155                 .name = "19eg",
 156         },
 157         {
 158                 .id = 0x59,
 159                 .name = "17eg",
 160         },
 161         {
 162                 .id = 0x61,
 163                 .name = "21dr",
 164         },
 165         {
 166                 .id = 0x63,
 167                 .name = "23dr",
 168         },
 169         {
 170                 .id = 0x65,
 171                 .name = "25dr",
 172         },
 173         {
 174                 .id = 0x64,
 175                 .name = "27dr",
 176         },
 177         {
 178                 .id = 0x60,
 179                 .name = "28dr",
 180         },
 181         {
 182                 .id = 0x62,
 183                 .name = "29dr",
 184         },
 185         {
 186                 .id = 0x66,
 187                 .name = "39dr",
 188         },
 189         {
 190                 .id = 0x7b,
 191                 .name = "48dr",
 192         },
 193         {
 194                 .id = 0x7e,
 195                 .name = "49dr",
 196         },
 197 };
 198 #endif
 199
 200 #define ZYNQMP_VERSION_SIZE             9
 201 #define ZYNQMP_PL_STATUS_BIT            9
 202 #define ZYNQMP_IPDIS_VCU_BIT            8
 203 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 204 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 205 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 206                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 207 #define MAX_VARIANTS_EV                 3
 208
 209 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 210         !defined(CONFIG_SPL_BUILD)
 211 static char *zynqmp_get_silicon_idcode_name(void)
 212 {
 213         u32 i, id, ver, j;
 214         char *buf;
 215         static char name[ZYNQMP_VERSION_SIZE];
 216         u32 ret_payload[PAYLOAD_ARG_CNT];
 217
 218         xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
 219
 220         /*
 221          * Firmware returns:
 222          * payload[0][31:0]  = status of the operation
 223          * payload[1]] = IDCODE
 224          * payload[2][19:0]  = Version
 225          * payload[2][28:20] = EXTENDED_IDCODE
 226          * payload[2][29] = PL_INIT
 227          */
 228
 229         /* Get IDCODE field */
 230         id = ret_payload[1];
 231         id &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | ZYNQMP_CSU_IDCODE_SVD_MASK;
 232         id >>=  ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 233
 234         /* Shift silicon version info */
 235         ver = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 236
 237         debug("%s, ID: 0x%0X, Ver: 0x%0X\r\n", __func__, id, ver);
 238
 239         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 240                 if (zynqmp_devices[i].id == id) {
 241                         if (zynqmp_devices[i].evexists &&
 242                             !(ver & ZYNQMP_PL_STATUS_MASK))
 243                                 break;
 244                         if (zynqmp_devices[i].ver == (ver &
 245                             ZYNQMP_CSU_VERSION_MASK))
 246                                 break;
 247                 }
 248         }
 249
 250         if (i >= ARRAY_SIZE(zynqmp_devices))
 251                 return "unknown";
 252
 253         strncat(name, "zu", 2);
 254         if (!zynqmp_devices[i].evexists ||
 255             (ver & ZYNQMP_PL_STATUS_MASK)) {
 256                 strncat(name, zynqmp_devices[i].name,
 257                         ZYNQMP_VERSION_SIZE - 3);
 258                 return name;
 259         }
 260
 261         /*
 262          * Here we are means, PL not powered up and ev variant
 263          * exists. So, we need to ignore VCU disable bit(8) in
 264          * version and findout if its CG or EG/EV variant.
 265          */
 266         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 267                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 268                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 269                         strncat(name, zynqmp_devices[i].name,
 270                                 ZYNQMP_VERSION_SIZE - 3);
 271                         break;
 272                 }
 273         }
 274
 275         if (j >= MAX_VARIANTS_EV)
 276                 return "unknown";
 277
 278         if (strstr(name, "eg") || strstr(name, "ev")) {
 279                 buf = strstr(name, "e");
 280                 *buf = '\0';
 281         }
 282
 283         return name;
 284 }
 285 #endif
 286
 287 int board_early_init_f(void)
 288 {
 289 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 290         int ret;
 291
 292         ret = psu_init();
 293         if (ret)
 294                 return ret;
 295
 296         /* Delay is required for clocks to be propagated */
 297         udelay(1000000);
 298 #endif
 299
 300 #ifdef CONFIG_DEBUG_UART
 301         /* Uart debug for sure */
 302         debug_uart_init();
 303         puts("Debug uart enabled\n"); /* or printch() */
 304 #endif
 305
 306         return 0;
 307 }
 308
 309 static int multi_boot(void)
 310 {
 311         u32 multiboot;
 312
 313         multiboot = readl(&csu_base->multi_boot);
 314
 315         printf("Multiboot:\t%d\n", multiboot);
 316
 317         return 0;
 318 }
 319
 320 #define PS_SYSMON_ANALOG_BUS_VAL        0x3210
 321 #define PS_SYSMON_ANALOG_BUS_REG        0xFFA50914
 322
 323 int board_init(void)
 324 {
 325 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 326         struct udevice *dev;
 327
 328         uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
 329         if (!dev)
 330                 panic("PMU Firmware device not found - Enable it");
 331 #endif
 332
 333 #if defined(CONFIG_SPL_BUILD)
 334         /* Check *at build time* if the filename is an non-empty string */
 335         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 336                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 337                                                 zynqmp_pm_cfg_obj_size);
 338 #endif
 339
 340         printf("EL Level:\tEL%d\n", current_el());
 341
 342         /* Bug in ROM sets wrong value in this register */
 343         writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
 344
 345 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 346     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 347     defined(CONFIG_SPL_BUILD))
 348         zynqmppl.name = zynqmp_get_silicon_idcode_name();
 349         printf("Chip ID:\t%s\n", zynqmppl.name);
 350         fpga_init();
 351         fpga_add(fpga_xilinx, &zynqmppl);
 352 #endif
 353
 354         if (current_el() == 3)
 355                 multi_boot();
 356
 357         return 0;
 358 }
 359
 360 int board_early_init_r(void)
 361 {
 362         u32 val;
 363
 364         if (current_el() != 3)
 365                 return 0;
 366
 367         val = readl(&crlapb_base->timestamp_ref_ctrl);
 368         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 369
 370         if (!val) {
 371                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 372                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 373                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 374
 375                 /* Program freq register in System counter */
 376                 writel(zynqmp_get_system_timer_freq(),
 377                        &iou_scntr_secure->base_frequency_id_register);
 378                 /* And enable system counter */
 379                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 380                        &iou_scntr_secure->counter_control_register);
 381         }
 382         return 0;
 383 }
 384
 385 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 386                          char *const argv[])
 387 {
 388         int ret = 0;
 389
 390         if (current_el() > 1) {
 391                 smp_kick_all_cpus();
 392                 dcache_disable();
 393                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 394                                     ES_TO_AARCH64);
 395         } else {
 396                 printf("FAIL: current EL is not above EL1\n");
 397                 ret = EINVAL;
 398         }
 399         return ret;
 400 }
 401
 402 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 403 int dram_init_banksize(void)
 404 {
 405         int ret;
 406
 407         ret = fdtdec_setup_memory_banksize();
 408         if (ret)
 409                 return ret;
 410
 411         mem_map_fill();
 412
 413         return 0;
 414 }
 415
 416 int dram_init(void)
 417 {
 418         if (fdtdec_setup_mem_size_base() != 0)
 419                 return -EINVAL;
 420
 421         return 0;
 422 }
 423 #else
 424 int dram_init_banksize(void)
 425 {
 426 #if defined(CONFIG_NR_DRAM_BANKS)
 427         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 428         gd->bd->bi_dram[0].size = get_effective_memsize();
 429 #endif
 430
 431         mem_map_fill();
 432
 433         return 0;
 434 }
 435
 436 int dram_init(void)
 437 {
 438         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 439                                     CONFIG_SYS_SDRAM_SIZE);
 440
 441         return 0;
 442 }
 443 #endif
 444
 445 void reset_cpu(ulong addr)
 446 {
 447 }
 448
 449 #if defined(CONFIG_BOARD_LATE_INIT)
 450 static const struct {
 451         u32 bit;
 452         const char *name;
 453 } reset_reasons[] = {
 454         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 455         { RESET_REASON_SOFT, "SOFT" },
 456         { RESET_REASON_SRST, "SRST" },
 457         { RESET_REASON_PSONLY, "PS-ONLY" },
 458         { RESET_REASON_PMU, "PMU" },
 459         { RESET_REASON_INTERNAL, "INTERNAL" },
 460         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 461         {}
 462 };
 463
 464 static int reset_reason(void)
 465 {
 466         u32 reg;
 467         int i, ret;
 468         const char *reason = NULL;
 469
 470         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 471         if (ret)
 472                 return -EINVAL;
 473
 474         puts("Reset reason:\t");
 475
 476         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 477                 if (reg & reset_reasons[i].bit) {
 478                         reason = reset_reasons[i].name;
 479                         printf("%s ", reset_reasons[i].name);
 480                         break;
 481                 }
 482         }
 483
 484         puts("\n");
 485
 486         env_set("reset_reason", reason);
 487
 488         ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
 489         if (ret)
 490                 return -EINVAL;
 491
 492         return ret;
 493 }
 494
 495 static int set_fdtfile(void)
 496 {
 497         char *compatible, *fdtfile;
 498         const char *suffix = ".dtb";
 499         const char *vendor = "xilinx/";
 500         int fdt_compat_len;
 501
 502         if (env_get("fdtfile"))
 503                 return 0;
 504
 505         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
 506                                          &fdt_compat_len);
 507         if (compatible && fdt_compat_len) {
 508                 char *name;
 509
 510                 debug("Compatible: %s\n", compatible);
 511
 512                 name = strchr(compatible, ',');
 513                 if (!name)
 514                         return -EINVAL;
 515
 516                 name++;
 517
 518                 fdtfile = calloc(1, strlen(vendor) + strlen(name) +
 519                                  strlen(suffix) + 1);
 520                 if (!fdtfile)
 521                         return -ENOMEM;
 522
 523                 sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
 524
 525                 env_set("fdtfile", fdtfile);
 526                 free(fdtfile);
 527         }
 528
 529         return 0;
 530 }
 531
 532 static u8 zynqmp_get_bootmode(void)
 533 {
 534         u8 bootmode;
 535         u32 reg = 0;
 536         int ret;
 537
 538         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 539         if (ret)
 540                 return -EINVAL;
 541
 542         if (reg >> BOOT_MODE_ALT_SHIFT)
 543                 reg >>= BOOT_MODE_ALT_SHIFT;
 544
 545         bootmode = reg & BOOT_MODES_MASK;
 546
 547         return bootmode;
 548 }
 549
 550 int board_late_init(void)
 551 {
 552         u8 bootmode;
 553         struct udevice *dev;
 554         int bootseq = -1;
 555         int bootseq_len = 0;
 556         int env_targets_len = 0;
 557         const char *mode;
 558         char *new_targets;
 559         char *env_targets;
 560         int ret;
 561
 562 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 563         usb_ether_init();
 564 #endif
 565
 566         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 567                 debug("Saved variables - Skipping\n");
 568                 return 0;
 569         }
 570
 571         if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
 572                 return 0;
 573
 574         ret = set_fdtfile();
 575         if (ret)
 576                 return ret;
 577
 578         bootmode = zynqmp_get_bootmode();
 579
 580         puts("Bootmode: ");
 581         switch (bootmode) {
 582         case USB_MODE:
 583                 puts("USB_MODE\n");
 584                 mode = "usb";
 585                 env_set("modeboot", "usb_dfu_spl");
 586                 break;
 587         case JTAG_MODE:
 588                 puts("JTAG_MODE\n");
 589                 mode = "jtag pxe dhcp";
 590                 env_set("modeboot", "jtagboot");
 591                 break;
 592         case QSPI_MODE_24BIT:
 593         case QSPI_MODE_32BIT:
 594                 mode = "qspi0";
 595                 puts("QSPI_MODE\n");
 596                 env_set("modeboot", "qspiboot");
 597                 break;
 598         case EMMC_MODE:
 599                 puts("EMMC_MODE\n");
 600                 if (uclass_get_device_by_name(UCLASS_MMC,
 601                                               "mmc@ff160000", &dev) &&
 602                     uclass_get_device_by_name(UCLASS_MMC,
 603                                               "sdhci@ff160000", &dev)) {
 604                         puts("Boot from EMMC but without SD0 enabled!\n");
 605                         return -1;
 606                 }
 607                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 608
 609                 mode = "mmc";
 610                 bootseq = dev->seq;
 611                 break;
 612         case SD_MODE:
 613                 puts("SD_MODE\n");
 614                 if (uclass_get_device_by_name(UCLASS_MMC,
 615                                               "mmc@ff160000", &dev) &&
 616                     uclass_get_device_by_name(UCLASS_MMC,
 617                                               "sdhci@ff160000", &dev)) {
 618                         puts("Boot from SD0 but without SD0 enabled!\n");
 619                         return -1;
 620                 }
 621                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 622
 623                 mode = "mmc";
 624                 bootseq = dev->seq;
 625                 env_set("modeboot", "sdboot");
 626                 break;
 627         case SD1_LSHFT_MODE:
 628                 puts("LVL_SHFT_");
 629                 /* fall through */
 630         case SD_MODE1:
 631                 puts("SD_MODE1\n");
 632                 if (uclass_get_device_by_name(UCLASS_MMC,
 633                                               "mmc@ff170000", &dev) &&
 634                     uclass_get_device_by_name(UCLASS_MMC,
 635                                               "sdhci@ff170000", &dev)) {
 636                         puts("Boot from SD1 but without SD1 enabled!\n");
 637                         return -1;
 638                 }
 639                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 640
 641                 mode = "mmc";
 642                 bootseq = dev->seq;
 643                 env_set("modeboot", "sdboot");
 644                 break;
 645         case NAND_MODE:
 646                 puts("NAND_MODE\n");
 647                 mode = "nand0";
 648                 env_set("modeboot", "nandboot");
 649                 break;
 650         default:
 651                 mode = "";
 652                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 653                 break;
 654         }
 655
 656         if (bootseq >= 0) {
 657                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 658                 debug("Bootseq len: %x\n", bootseq_len);
 659         }
 660
 661         /*
 662          * One terminating char + one byte for space between mode
 663          * and default boot_targets
 664          */
 665         env_targets = env_get("boot_targets");
 666         if (env_targets)
 667                 env_targets_len = strlen(env_targets);
 668
 669         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 670                              bootseq_len);
 671         if (!new_targets)
 672                 return -ENOMEM;
 673
 674         if (bootseq >= 0)
 675                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 676                         env_targets ? env_targets : "");
 677         else
 678                 sprintf(new_targets, "%s %s", mode,
 679                         env_targets ? env_targets : "");
 680
 681         env_set("boot_targets", new_targets);
 682
 683         reset_reason();
 684
 685         return board_late_init_xilinx();
 686 }
 687 #endif
 688
 689 int checkboard(void)
 690 {
 691         puts("Board: Xilinx ZynqMP\n");
 692         return 0;
 693 }