1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/psu_init_gpl.h>
18 #include <dm/device.h>
19 #include <dm/uclass.h>
21 #include <dwc3-uboot.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
29 static struct udevice *watchdog_dev;
32 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
33 !defined(CONFIG_SPL_BUILD)
34 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
41 } zynqmp_devices[] = {
130 { /* For testing purpose only */
174 int chip_id(unsigned char id)
179 if (current_el() != 3) {
180 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
189 * regs[0][31:0] = status of the operation
190 * regs[0][63:32] = CSU.IDCODE register
191 * regs[1][31:0] = CSU.version register
192 * regs[1][63:32] = CSU.IDCODE2 register
196 regs.regs[0] = upper_32_bits(regs.regs[0]);
197 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
198 ZYNQMP_CSU_IDCODE_SVD_MASK;
199 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
203 regs.regs[1] = lower_32_bits(regs.regs[1]);
204 regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
208 regs.regs[1] = lower_32_bits(regs.regs[1]);
209 regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
213 printf("%s, Invalid Req:0x%x\n", __func__, id);
218 val = readl(ZYNQMP_CSU_IDCODE_ADDR);
219 val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
220 ZYNQMP_CSU_IDCODE_SVD_MASK;
221 val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
224 val = readl(ZYNQMP_CSU_VER_ADDR);
225 val &= ZYNQMP_CSU_SILICON_VER_MASK;
228 printf("%s, Invalid Req:0x%x\n", __func__, id);
235 #define ZYNQMP_VERSION_SIZE 9
236 #define ZYNQMP_PL_STATUS_BIT 9
237 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
238 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
240 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
241 !defined(CONFIG_SPL_BUILD)
242 static char *zynqmp_get_silicon_idcode_name(void)
246 static char name[ZYNQMP_VERSION_SIZE];
248 id = chip_id(IDCODE);
249 ver = chip_id(IDCODE2);
251 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
252 if ((zynqmp_devices[i].id == id) &&
253 (zynqmp_devices[i].ver == (ver &
254 ZYNQMP_CSU_VERSION_MASK))) {
255 strncat(name, "zu", 2);
256 strncat(name, zynqmp_devices[i].name,
257 ZYNQMP_VERSION_SIZE - 3);
262 if (i >= ARRAY_SIZE(zynqmp_devices))
265 if (!zynqmp_devices[i].evexists)
268 if (ver & ZYNQMP_PL_STATUS_MASK)
271 if (strstr(name, "eg") || strstr(name, "ev")) {
272 buf = strstr(name, "e");
280 int board_early_init_f(void)
283 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
286 pm_api_version = zynqmp_pmufw_version();
287 printf("PMUFW:\tv%d.%d\n",
288 pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
289 pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
291 if (pm_api_version < ZYNQMP_PM_VERSION)
292 panic("PMUFW version error. Expected: v%d.%d\n",
293 ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
296 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
300 #if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
301 /* bss is not cleared at time when watchdog_reset() is called */
310 printf("EL Level:\tEL%d\n", current_el());
312 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
313 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
314 defined(CONFIG_SPL_BUILD))
315 if (current_el() != 3) {
316 zynqmppl.name = zynqmp_get_silicon_idcode_name();
317 printf("Chip ID:\t%s\n", zynqmppl.name);
319 fpga_add(fpga_xilinx, &zynqmppl);
323 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
324 if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
325 debug("Watchdog: Not found by seq!\n");
326 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
327 puts("Watchdog: Not found!\n");
332 wdt_start(watchdog_dev, 0, 0);
333 puts("Watchdog: Started\n");
339 #ifdef CONFIG_WATCHDOG
340 /* Called by macro WATCHDOG_RESET */
341 void watchdog_reset(void)
343 # if !defined(CONFIG_SPL_BUILD)
344 static ulong next_reset;
350 now = timer_get_us();
352 /* Do not reset the watchdog too often */
353 if (now > next_reset) {
354 wdt_reset(watchdog_dev);
355 next_reset = now + 1000;
361 int board_early_init_r(void)
365 if (current_el() != 3)
368 val = readl(&crlapb_base->timestamp_ref_ctrl);
369 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
372 val = readl(&crlapb_base->timestamp_ref_ctrl);
373 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
374 writel(val, &crlapb_base->timestamp_ref_ctrl);
376 /* Program freq register in System counter */
377 writel(zynqmp_get_system_timer_freq(),
378 &iou_scntr_secure->base_frequency_id_register);
379 /* And enable system counter */
380 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
381 &iou_scntr_secure->counter_control_register);
386 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
388 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
389 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
390 defined(CONFIG_ZYNQ_EEPROM_BUS)
391 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
393 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
394 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
396 printf("I2C EEPROM MAC address read failed\n");
402 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
407 if (current_el() > 1) {
410 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
413 printf("FAIL: current EL is not above EL1\n");
419 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
420 int dram_init_banksize(void)
424 ret = fdtdec_setup_memory_banksize();
435 if (fdtdec_setup_mem_size_base() != 0)
441 int dram_init_banksize(void)
443 #if defined(CONFIG_NR_DRAM_BANKS)
444 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
445 gd->bd->bi_dram[0].size = get_effective_memsize();
455 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
456 CONFIG_SYS_SDRAM_SIZE);
462 void reset_cpu(ulong addr)
466 static const struct {
469 } reset_reasons[] = {
470 { RESET_REASON_DEBUG_SYS, "DEBUG" },
471 { RESET_REASON_SOFT, "SOFT" },
472 { RESET_REASON_SRST, "SRST" },
473 { RESET_REASON_PSONLY, "PS-ONLY" },
474 { RESET_REASON_PMU, "PMU" },
475 { RESET_REASON_INTERNAL, "INTERNAL" },
476 { RESET_REASON_EXTERNAL, "EXTERNAL" },
480 static u32 reset_reason(void)
484 const char *reason = NULL;
486 ret = readl(&crlapb_base->reset_reason);
488 puts("Reset reason:\t");
490 for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
491 if (ret & reset_reasons[i].bit) {
492 reason = reset_reasons[i].name;
493 printf("%s ", reset_reasons[i].name);
500 env_set("reset_reason", reason);
502 writel(~0, &crlapb_base->reset_reason);
507 int board_late_init(void)
514 int env_targets_len = 0;
520 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
521 debug("Saved variables - Skipping\n");
525 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
529 if (reg >> BOOT_MODE_ALT_SHIFT)
530 reg >>= BOOT_MODE_ALT_SHIFT;
532 bootmode = reg & BOOT_MODES_MASK;
539 env_set("modeboot", "usb_dfu_spl");
544 env_set("modeboot", "jtagboot");
546 case QSPI_MODE_24BIT:
547 case QSPI_MODE_32BIT:
550 env_set("modeboot", "qspiboot");
555 env_set("modeboot", "emmcboot");
559 if (uclass_get_device_by_name(UCLASS_MMC,
560 "sdhci@ff160000", &dev)) {
561 puts("Boot from SD0 but without SD0 enabled!\n");
564 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
568 env_set("modeboot", "sdboot");
575 if (uclass_get_device_by_name(UCLASS_MMC,
576 "sdhci@ff170000", &dev)) {
577 puts("Boot from SD1 but without SD1 enabled!\n");
580 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
584 env_set("modeboot", "sdboot");
589 env_set("modeboot", "nandboot");
593 printf("Invalid Boot Mode:0x%x\n", bootmode);
598 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
599 debug("Bootseq len: %x\n", bootseq_len);
603 * One terminating char + one byte for space between mode
604 * and default boot_targets
606 env_targets = env_get("boot_targets");
608 env_targets_len = strlen(env_targets);
610 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
616 sprintf(new_targets, "%s%x %s", mode, bootseq,
617 env_targets ? env_targets : "");
619 sprintf(new_targets, "%s %s", mode,
620 env_targets ? env_targets : "");
622 env_set("boot_targets", new_targets);
631 puts("Board: Xilinx ZynqMP\n");