board/xilinx/zynqmp/zynqmp.c

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <sata.h>
  10 #include <ahci.h>
  11 #include <scsi.h>
  12 #include <malloc.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/io.h>
  17 #include <usb.h>
  18 #include <dwc3-uboot.h>
  19 #include <zynqmppl.h>
  20 #include <i2c.h>
  21 #include <g_dnl.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  26     !defined(CONFIG_SPL_BUILD)
  27 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  28
  29 static const struct {
  30         uint32_t id;
  31         char *name;
  32 } zynqmp_devices[] = {
  33         {
  34                 .id = 0x10,
  35                 .name = "3eg",
  36         },
  37         {
  38                 .id = 0x11,
  39                 .name = "2eg",
  40         },
  41         {
  42                 .id = 0x20,
  43                 .name = "5ev",
  44         },
  45         {
  46                 .id = 0x21,
  47                 .name = "4ev",
  48         },
  49         {
  50                 .id = 0x30,
  51                 .name = "7ev",
  52         },
  53         {
  54                 .id = 0x38,
  55                 .name = "9eg",
  56         },
  57         {
  58                 .id = 0x39,
  59                 .name = "6eg",
  60         },
  61         {
  62                 .id = 0x40,
  63                 .name = "11eg",
  64         },
  65         {
  66                 .id = 0x50,
  67                 .name = "15eg",
  68         },
  69         {
  70                 .id = 0x58,
  71                 .name = "19eg",
  72         },
  73         {
  74                 .id = 0x59,
  75                 .name = "17eg",
  76         },
  77 };
  78
  79 static int chip_id(void)
  80 {
  81         struct pt_regs regs;
  82         regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
  83         regs.regs[1] = 0;
  84         regs.regs[2] = 0;
  85         regs.regs[3] = 0;
  86
  87         smc_call(&regs);
  88
  89         /*
  90          * SMC returns:
  91          * regs[0][31:0]  = status of the operation
  92          * regs[0][63:32] = CSU.IDCODE register
  93          * regs[1][31:0]  = CSU.version register
  94          */
  95         regs.regs[0] = upper_32_bits(regs.regs[0]);
  96         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
  97                         ZYNQMP_CSU_IDCODE_SVD_MASK;
  98         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
  99
 100         return regs.regs[0];
 101 }
 102
 103 static char *zynqmp_get_silicon_idcode_name(void)
 104 {
 105         uint32_t i, id;
 106
 107         id = chip_id();
 108         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 109                 if (zynqmp_devices[i].id == id)
 110                         return zynqmp_devices[i].name;
 111         }
 112         return "unknown";
 113 }
 114 #endif
 115
 116 #define ZYNQMP_VERSION_SIZE     9
 117
 118 int board_init(void)
 119 {
 120         printf("EL Level:\tEL%d\n", current_el());
 121
 122 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 123     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 124     defined(CONFIG_SPL_BUILD))
 125         if (current_el() != 3) {
 126                 static char version[ZYNQMP_VERSION_SIZE];
 127
 128                 strncat(version, "xczu", ZYNQMP_VERSION_SIZE);
 129                 zynqmppl.name = strncat(version,
 130                                         zynqmp_get_silicon_idcode_name(),
 131                                         ZYNQMP_VERSION_SIZE);
 132                 printf("Chip ID:\t%s\n", zynqmppl.name);
 133                 fpga_init();
 134                 fpga_add(fpga_xilinx, &zynqmppl);
 135         }
 136 #endif
 137
 138         return 0;
 139 }
 140
 141 int board_early_init_r(void)
 142 {
 143         u32 val;
 144
 145         if (current_el() == 3) {
 146                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 147                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 148                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 149
 150                 /* Program freq register in System counter */
 151                 writel(zynqmp_get_system_timer_freq(),
 152                        &iou_scntr_secure->base_frequency_id_register);
 153                 /* And enable system counter */
 154                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 155                        &iou_scntr_secure->counter_control_register);
 156         }
 157         /* Program freq register in System counter and enable system counter */
 158         writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
 159         writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
 160                ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 161                &iou_scntr->counter_control_register);
 162
 163         return 0;
 164 }
 165
 166 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 167 {
 168 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 169     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
 170     defined(CONFIG_ZYNQ_EEPROM_BUS)
 171         i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
 172
 173         if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 174                         CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 175                         ethaddr, 6))
 176                 printf("I2C EEPROM MAC address read failed\n");
 177 #endif
 178
 179         return 0;
 180 }
 181
 182 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 183 /*
 184  * fdt_get_reg - Fill buffer by information from DT
 185  */
 186 static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
 187                                const u32 *cell, int n)
 188 {
 189         int i = 0, b, banks;
 190         int parent_offset = fdt_parent_offset(fdt, nodeoffset);
 191         int address_cells = fdt_address_cells(fdt, parent_offset);
 192         int size_cells = fdt_size_cells(fdt, parent_offset);
 193         char *p = buf;
 194         u64 val;
 195         u64 vals;
 196
 197         debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
 198               __func__, address_cells, size_cells, buf, cell);
 199
 200         /* Check memory bank setup */
 201         banks = n % (address_cells + size_cells);
 202         if (banks)
 203                 panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
 204                       n, address_cells, size_cells);
 205
 206         banks = n / (address_cells + size_cells);
 207
 208         for (b = 0; b < banks; b++) {
 209                 debug("%s: Bank #%d:\n", __func__, b);
 210                 if (address_cells == 2) {
 211                         val = cell[i + 1];
 212                         val <<= 32;
 213                         val |= cell[i];
 214                         val = fdt64_to_cpu(val);
 215                         debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
 216                               __func__, val, p, &cell[i]);
 217                         *(phys_addr_t *)p = val;
 218                 } else {
 219                         debug("%s: addr32=%x, ptr=%p\n",
 220                               __func__, fdt32_to_cpu(cell[i]), p);
 221                         *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
 222                 }
 223                 p += sizeof(phys_addr_t);
 224                 i += address_cells;
 225
 226                 debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
 227                       sizeof(phys_addr_t));
 228
 229                 if (size_cells == 2) {
 230                         vals = cell[i + 1];
 231                         vals <<= 32;
 232                         vals |= cell[i];
 233                         vals = fdt64_to_cpu(vals);
 234
 235                         debug("%s: size64=%llx, ptr=%p, cell=%p\n",
 236                               __func__, vals, p, &cell[i]);
 237                         *(phys_size_t *)p = vals;
 238                 } else {
 239                         debug("%s: size32=%x, ptr=%p\n",
 240                               __func__, fdt32_to_cpu(cell[i]), p);
 241                         *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
 242                 }
 243                 p += sizeof(phys_size_t);
 244                 i += size_cells;
 245
 246                 debug("%s: ps=%p, i=%x, size=%zu\n",
 247                       __func__, p, i, sizeof(phys_size_t));
 248         }
 249
 250         /* Return the first address size */
 251         return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
 252 }
 253
 254 #define FDT_REG_SIZE  sizeof(u32)
 255 /* Temp location for sharing data for storing */
 256 /* Up to 64-bit address + 64-bit size */
 257 static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
 258
 259 void dram_init_banksize(void)
 260 {
 261         int bank;
 262
 263         memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
 264
 265         for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
 266                 debug("Bank #%d: start %llx\n", bank,
 267                       (unsigned long long)gd->bd->bi_dram[bank].start);
 268                 debug("Bank #%d: size %llx\n", bank,
 269                       (unsigned long long)gd->bd->bi_dram[bank].size);
 270         }
 271 }
 272
 273 int dram_init(void)
 274 {
 275         int node, len;
 276         const void *blob = gd->fdt_blob;
 277         const u32 *cell;
 278
 279         memset(&tmp, 0, sizeof(tmp));
 280
 281         /* find or create "/memory" node. */
 282         node = fdt_subnode_offset(blob, 0, "memory");
 283         if (node < 0) {
 284                 printf("%s: Can't get memory node\n", __func__);
 285                 return node;
 286         }
 287
 288         /* Get pointer to cells and lenght of it */
 289         cell = fdt_getprop(blob, node, "reg", &len);
 290         if (!cell) {
 291                 printf("%s: Can't get reg property\n", __func__);
 292                 return -1;
 293         }
 294
 295         gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
 296
 297         debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
 298
 299         return 0;
 300 }
 301 #else
 302 int dram_init(void)
 303 {
 304         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 305
 306         return 0;
 307 }
 308 #endif
 309
 310 void reset_cpu(ulong addr)
 311 {
 312 }
 313
 314 #ifdef CONFIG_SCSI_AHCI_PLAT
 315 void scsi_init(void)
 316 {
 317 #if defined(CONFIG_SATA_CEVA)
 318         init_sata(0);
 319 #endif
 320         ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
 321         scsi_scan(1);
 322 }
 323 #endif
 324
 325 int board_late_init(void)
 326 {
 327         u32 reg = 0;
 328         u8 bootmode;
 329         const char *mode;
 330         char *new_targets;
 331
 332         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 333                 debug("Saved variables - Skipping\n");
 334                 return 0;
 335         }
 336
 337         reg = readl(&crlapb_base->boot_mode);
 338         bootmode = reg & BOOT_MODES_MASK;
 339
 340         puts("Bootmode: ");
 341         switch (bootmode) {
 342         case USB_MODE:
 343                 puts("USB_MODE\n");
 344                 mode = "usb";
 345                 break;
 346         case JTAG_MODE:
 347                 puts("JTAG_MODE\n");
 348                 mode = "pxe dhcp";
 349                 break;
 350         case QSPI_MODE_24BIT:
 351         case QSPI_MODE_32BIT:
 352                 mode = "qspi0";
 353                 puts("QSPI_MODE\n");
 354                 break;
 355         case EMMC_MODE:
 356                 puts("EMMC_MODE\n");
 357                 mode = "mmc0";
 358                 break;
 359         case SD_MODE:
 360                 puts("SD_MODE\n");
 361                 mode = "mmc0";
 362                 break;
 363         case SD_MODE1:
 364                 puts("SD_MODE1\n");
 365 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
 366                 mode = "mmc1";
 367 #else
 368                 mode = "mmc0";
 369 #endif
 370                 break;
 371         case NAND_MODE:
 372                 puts("NAND_MODE\n");
 373                 mode = "nand0";
 374                 break;
 375         default:
 376                 mode = "";
 377                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 378                 break;
 379         }
 380
 381         /*
 382          * One terminating char + one byte for space between mode
 383          * and default boot_targets
 384          */
 385         new_targets = calloc(1, strlen(mode) +
 386                                 strlen(getenv("boot_targets")) + 2);
 387
 388         sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
 389         setenv("boot_targets", new_targets);
 390
 391         return 0;
 392 }
 393
 394 int checkboard(void)
 395 {
 396         puts("Board: Xilinx ZynqMP\n");
 397         return 0;
 398 }
 399
 400 #ifdef CONFIG_USB_DWC3
 401 static struct dwc3_device dwc3_device_data0 = {
 402         .maximum_speed = USB_SPEED_HIGH,
 403         .base = ZYNQMP_USB0_XHCI_BASEADDR,
 404         .dr_mode = USB_DR_MODE_PERIPHERAL,
 405         .index = 0,
 406 };
 407
 408 static struct dwc3_device dwc3_device_data1 = {
 409         .maximum_speed = USB_SPEED_HIGH,
 410         .base = ZYNQMP_USB1_XHCI_BASEADDR,
 411         .dr_mode = USB_DR_MODE_PERIPHERAL,
 412         .index = 1,
 413 };
 414
 415 int usb_gadget_handle_interrupts(int index)
 416 {
 417         dwc3_uboot_handle_interrupt(index);
 418         return 0;
 419 }
 420
 421 int board_usb_init(int index, enum usb_init_type init)
 422 {
 423         debug("%s: index %x\n", __func__, index);
 424
 425 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
 426         g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
 427 #endif
 428
 429         switch (index) {
 430         case 0:
 431                 return dwc3_uboot_init(&dwc3_device_data0);
 432         case 1:
 433                 return dwc3_uboot_init(&dwc3_device_data1);
 434         };
 435
 436         return -1;
 437 }
 438
 439 int board_usb_cleanup(int index, enum usb_init_type init)
 440 {
 441         dwc3_uboot_exit(index);
 442         return 0;
 443 }
 444 #endif