board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cpu_func.h>
  10 #include <debug_uart.h>
  11 #include <dfu.h>
  12 #include <env.h>
  13 #include <env_internal.h>
  14 #include <init.h>
  15 #include <image.h>
  16 #include <lmb.h>
  17 #include <log.h>
  18 #include <net.h>
  19 #include <sata.h>
  20 #include <ahci.h>
  21 #include <scsi.h>
  22 #include <malloc.h>
  23 #include <memalign.h>
  24 #include <wdt.h>
  25 #include <asm/arch/clk.h>
  26 #include <asm/arch/hardware.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/psu_init_gpl.h>
  29 #include <asm/cache.h>
  30 #include <asm/global_data.h>
  31 #include <asm/io.h>
  32 #include <asm/ptrace.h>
  33 #include <dm/device.h>
  34 #include <dm/uclass.h>
  35 #include <usb.h>
  36 #include <dwc3-uboot.h>
  37 #include <zynqmppl.h>
  38 #include <zynqmp_firmware.h>
  39 #include <g_dnl.h>
  40 #include <linux/bitops.h>
  41 #include <linux/delay.h>
  42 #include <linux/sizes.h>
  43 #include "../common/board.h"
  44
  45 #include "pm_cfg_obj.h"
  46
  47 #define ZYNQMP_VERSION_SIZE     7
  48 #define EFUSE_VCU_DIS_MASK      0x100
  49 #define EFUSE_VCU_DIS_SHIFT     8
  50 #define EFUSE_GPU_DIS_MASK      0x20
  51 #define EFUSE_GPU_DIS_SHIFT     5
  52 #define IDCODE2_PL_INIT_MASK    0x200
  53 #define IDCODE2_PL_INIT_SHIFT   9
  54
  55 DECLARE_GLOBAL_DATA_PTR;
  56
  57 #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
  58 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  59
  60 enum {
  61         ZYNQMP_VARIANT_EG = BIT(0U),
  62         ZYNQMP_VARIANT_EV = BIT(1U),
  63         ZYNQMP_VARIANT_CG = BIT(2U),
  64         ZYNQMP_VARIANT_DR = BIT(3U),
  65 };
  66
  67 static const struct {
  68         u32 id;
  69         u8 device;
  70         u8 variants;
  71 } zynqmp_devices[] = {
  72         {
  73                 .id = 0x04688093,
  74                 .device = 1,
  75                 .variants = ZYNQMP_VARIANT_EG,
  76         },
  77         {
  78                 .id = 0x04711093,
  79                 .device = 2,
  80                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  81         },
  82         {
  83                 .id = 0x04710093,
  84                 .device = 3,
  85                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  86         },
  87         {
  88                 .id = 0x04721093,
  89                 .device = 4,
  90                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  91                         ZYNQMP_VARIANT_EV,
  92         },
  93         {
  94                 .id = 0x04720093,
  95                 .device = 5,
  96                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  97                         ZYNQMP_VARIANT_EV,
  98         },
  99         {
 100                 .id = 0x04739093,
 101                 .device = 6,
 102                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 103         },
 104         {
 105                 .id = 0x04730093,
 106                 .device = 7,
 107                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
 108                         ZYNQMP_VARIANT_EV,
 109         },
 110         {
 111                 .id = 0x04738093,
 112                 .device = 9,
 113                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 114         },
 115         {
 116                 .id = 0x04740093,
 117                 .device = 11,
 118                 .variants = ZYNQMP_VARIANT_EG,
 119         },
 120         {
 121                 .id = 0x04750093,
 122                 .device = 15,
 123                 .variants = ZYNQMP_VARIANT_EG,
 124         },
 125         {
 126                 .id = 0x04759093,
 127                 .device = 17,
 128                 .variants = ZYNQMP_VARIANT_EG,
 129         },
 130         {
 131                 .id = 0x04758093,
 132                 .device = 19,
 133                 .variants = ZYNQMP_VARIANT_EG,
 134         },
 135         {
 136                 .id = 0x047E1093,
 137                 .device = 21,
 138                 .variants = ZYNQMP_VARIANT_DR,
 139         },
 140         {
 141                 .id = 0x047E3093,
 142                 .device = 23,
 143                 .variants = ZYNQMP_VARIANT_DR,
 144         },
 145         {
 146                 .id = 0x047E5093,
 147                 .device = 25,
 148                 .variants = ZYNQMP_VARIANT_DR,
 149         },
 150         {
 151                 .id = 0x047E4093,
 152                 .device = 27,
 153                 .variants = ZYNQMP_VARIANT_DR,
 154         },
 155         {
 156                 .id = 0x047E0093,
 157                 .device = 28,
 158                 .variants = ZYNQMP_VARIANT_DR,
 159         },
 160         {
 161                 .id = 0x047E2093,
 162                 .device = 29,
 163                 .variants = ZYNQMP_VARIANT_DR,
 164         },
 165         {
 166                 .id = 0x047E6093,
 167                 .device = 39,
 168                 .variants = ZYNQMP_VARIANT_DR,
 169         },
 170         {
 171                 .id = 0x047FD093,
 172                 .device = 43,
 173                 .variants = ZYNQMP_VARIANT_DR,
 174         },
 175         {
 176                 .id = 0x047F8093,
 177                 .device = 46,
 178                 .variants = ZYNQMP_VARIANT_DR,
 179         },
 180         {
 181                 .id = 0x047FF093,
 182                 .device = 47,
 183                 .variants = ZYNQMP_VARIANT_DR,
 184         },
 185         {
 186                 .id = 0x047FB093,
 187                 .device = 48,
 188                 .variants = ZYNQMP_VARIANT_DR,
 189         },
 190         {
 191                 .id = 0x047FE093,
 192                 .device = 49,
 193                 .variants = ZYNQMP_VARIANT_DR,
 194         },
 195         {
 196                 .id = 0x046d0093,
 197                 .device = 67,
 198                 .variants = ZYNQMP_VARIANT_DR,
 199         },
 200 };
 201
 202 static const struct {
 203         u32 id;
 204         char *name;
 205 } zynqmp_svd_devices[] = {
 206         {
 207                 .id = 0x04714093,
 208                 .name = "xck24"
 209         },
 210         {
 211                 .id = 0x04724093,
 212                 .name = "xck26",
 213         },
 214 };
 215
 216 static char *zynqmp_detect_svd_name(u32 idcode)
 217 {
 218         u32 i;
 219
 220         for (i = 0; i < ARRAY_SIZE(zynqmp_svd_devices); i++) {
 221                 if (zynqmp_svd_devices[i].id == (idcode & 0x0FFFFFFF))
 222                         return zynqmp_svd_devices[i].name;
 223         }
 224
 225         return "unknown";
 226 }
 227
 228 static char *zynqmp_get_silicon_idcode_name(void)
 229 {
 230         u32 i;
 231         u32 idcode, idcode2;
 232         char name[ZYNQMP_VERSION_SIZE];
 233         u32 ret_payload[PAYLOAD_ARG_CNT];
 234         int ret;
 235
 236         ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
 237         if (ret) {
 238                 debug("%s: Getting chipid failed\n", __func__);
 239                 return "unknown";
 240         }
 241
 242         /*
 243          * Firmware returns:
 244          * payload[0][31:0]  = status of the operation
 245          * payload[1]] = IDCODE
 246          * payload[2][19:0]  = Version
 247          * payload[2][28:20] = EXTENDED_IDCODE
 248          * payload[2][29] = PL_INIT
 249          */
 250
 251         idcode  = ret_payload[1];
 252         idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 253         debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode,
 254               idcode2);
 255
 256         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 257                 if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
 258                         break;
 259         }
 260
 261         if (i >= ARRAY_SIZE(zynqmp_devices))
 262                 return zynqmp_detect_svd_name(idcode);
 263
 264         /* Add device prefix to the name */
 265         ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
 266                        zynqmp_devices[i].device);
 267         if (ret < 0)
 268                 return "unknown";
 269
 270         if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
 271                 /* Devices with EV variant might be EG/CG/EV family */
 272                 if (idcode2 & IDCODE2_PL_INIT_MASK) {
 273                         u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
 274                                       EFUSE_VCU_DIS_SHIFT) << 1 |
 275                                      ((idcode2 & EFUSE_GPU_DIS_MASK) >>
 276                                       EFUSE_GPU_DIS_SHIFT);
 277
 278                         /*
 279                          * Get family name based on extended idcode values as
 280                          * determined on UG1087, EXTENDED_IDCODE register
 281                          * description
 282                          */
 283                         switch (family) {
 284                         case 0x00:
 285                                 strncat(name, "ev", 2);
 286                                 break;
 287                         case 0x10:
 288                                 strncat(name, "eg", 2);
 289                                 break;
 290                         case 0x11:
 291                                 strncat(name, "cg", 2);
 292                                 break;
 293                         default:
 294                                 /* Do not append family name*/
 295                                 break;
 296                         }
 297                 } else {
 298                         /*
 299                          * When PL powered down the VCU Disable efuse cannot be
 300                          * read. So, ignore the bit and just findout if it is CG
 301                          * or EG/EV variant.
 302                          */
 303                         strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
 304                                 "e", 2);
 305                 }
 306         } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
 307                 /* Devices with CG variant might be EG or CG family */
 308                 strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
 309         } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
 310                 strncat(name, "eg", 2);
 311         } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
 312                 strncat(name, "dr", 2);
 313         } else {
 314                 debug("Variant not identified\n");
 315         }
 316
 317         return strdup(name);
 318 }
 319 #endif
 320
 321 int __maybe_unused psu_uboot_init(void)
 322 {
 323         int ret;
 324
 325         ret = psu_init();
 326         if (ret)
 327                 return ret;
 328
 329         /*
 330          * PS_SYSMON_ANALOG_BUS register determines mapping between SysMon
 331          * supply sense channel to SysMon supply registers inside the IP.
 332          * This register must be programmed to complete SysMon IP
 333          * configuration. The default register configuration after
 334          * power-up is incorrect. Hence, fix this by writing the
 335          * correct value - 0x3210.
 336          */
 337         writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
 338                ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
 339
 340         /* Delay is required for clocks to be propagated */
 341         udelay(1000000);
 342
 343         return 0;
 344 }
 345
 346 #if !defined(CONFIG_SPL_BUILD)
 347 # if defined(CONFIG_DEBUG_UART_BOARD_INIT)
 348 void board_debug_uart_init(void)
 349 {
 350 #  if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 351         psu_uboot_init();
 352 #  endif
 353 }
 354 # endif
 355
 356 # if defined(CONFIG_BOARD_EARLY_INIT_F)
 357 int board_early_init_f(void)
 358 {
 359         int ret = 0;
 360 #  if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED) && !defined(CONFIG_DEBUG_UART_BOARD_INIT)
 361         ret = psu_uboot_init();
 362 #  endif
 363         return ret;
 364 }
 365 # endif
 366 #endif
 367
 368 static int multi_boot(void)
 369 {
 370         u32 multiboot = 0;
 371         int ret;
 372
 373         ret = zynqmp_mmio_read((ulong)&csu_base->multi_boot, &multiboot);
 374         if (ret)
 375                 return -EINVAL;
 376
 377         return multiboot;
 378 }
 379
 380 #if defined(CONFIG_SPL_BUILD)
 381 static void restore_jtag(void)
 382 {
 383         if (current_el() != 3)
 384                 return;
 385
 386         writel(CSU_JTAG_SEC_GATE_DISABLE, &csu_base->jtag_sec);
 387         writel(CSU_JTAG_DAP_ENABLE_DEBUG, &csu_base->jtag_dap_cfg);
 388         writel(CSU_JTAG_CHAIN_WR_SETUP, &csu_base->jtag_chain_status_wr);
 389         writel(CRLAPB_DBG_LPD_CTRL_SETUP_CLK, &crlapb_base->dbg_lpd_ctrl);
 390         writel(CRLAPB_RST_LPD_DBG_RESET, &crlapb_base->rst_lpd_dbg);
 391         writel(CSU_PCAP_PROG_RELEASE_PL, &csu_base->pcap_prog);
 392 }
 393 #endif
 394
 395 static void print_secure_boot(void)
 396 {
 397         u32 status = 0;
 398
 399         if (zynqmp_mmio_read((ulong)&csu_base->status, &status))
 400                 return;
 401
 402         printf("Secure Boot:\t%sauthenticated, %sencrypted\n",
 403                status & ZYNQMP_CSU_STATUS_AUTHENTICATED ? "" : "not ",
 404                status & ZYNQMP_CSU_STATUS_ENCRYPTED ? "" : "not ");
 405 }
 406
 407 int board_init(void)
 408 {
 409 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 410         struct udevice *dev;
 411
 412         uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
 413         if (!dev)
 414                 panic("PMU Firmware device not found - Enable it");
 415 #endif
 416
 417 #if defined(CONFIG_SPL_BUILD)
 418         /* Check *at build time* if the filename is an non-empty string */
 419         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 420                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 421                                                 zynqmp_pm_cfg_obj_size);
 422         printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
 423
 424         /* the CSU disables the JTAG interface when secure boot is enabled */
 425         if (CONFIG_IS_ENABLED(ZYNQMP_RESTORE_JTAG))
 426                 restore_jtag();
 427 #else
 428         if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
 429                 xilinx_read_eeprom();
 430 #endif
 431
 432         printf("EL Level:\tEL%d\n", current_el());
 433
 434 #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
 435         zynqmppl.name = zynqmp_get_silicon_idcode_name();
 436         printf("Chip ID:\t%s\n", zynqmppl.name);
 437         fpga_init();
 438         fpga_add(fpga_xilinx, &zynqmppl);
 439 #endif
 440
 441         /* display secure boot information */
 442         print_secure_boot();
 443         if (current_el() == 3)
 444                 printf("Multiboot:\t%d\n", multi_boot());
 445
 446         return 0;
 447 }
 448
 449 int board_early_init_r(void)
 450 {
 451         u32 val;
 452
 453         if (current_el() != 3)
 454                 return 0;
 455
 456         val = readl(&crlapb_base->timestamp_ref_ctrl);
 457         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 458
 459         if (!val) {
 460                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 461                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 462                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 463
 464                 /* Program freq register in System counter */
 465                 writel(zynqmp_get_system_timer_freq(),
 466                        &iou_scntr_secure->base_frequency_id_register);
 467                 /* And enable system counter */
 468                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 469                        &iou_scntr_secure->counter_control_register);
 470         }
 471         return 0;
 472 }
 473
 474 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 475                          char *const argv[])
 476 {
 477         int ret = 0;
 478
 479         if (current_el() > 1) {
 480                 smp_kick_all_cpus();
 481                 dcache_disable();
 482                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 483                                     ES_TO_AARCH64);
 484         } else {
 485                 printf("FAIL: current EL is not above EL1\n");
 486                 ret = EINVAL;
 487         }
 488         return ret;
 489 }
 490
 491 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 492 int dram_init_banksize(void)
 493 {
 494         int ret;
 495
 496         ret = fdtdec_setup_memory_banksize();
 497         if (ret)
 498                 return ret;
 499
 500         mem_map_fill();
 501
 502         return 0;
 503 }
 504
 505 int dram_init(void)
 506 {
 507         if (fdtdec_setup_mem_size_base() != 0)
 508                 return -EINVAL;
 509
 510         return 0;
 511 }
 512
 513 ulong board_get_usable_ram_top(ulong total_size)
 514 {
 515         phys_size_t size;
 516         phys_addr_t reg;
 517         struct lmb lmb;
 518
 519         if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8))
 520                 panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob);
 521
 522         /* found enough not-reserved memory to relocated U-Boot */
 523         lmb_init(&lmb);
 524         lmb_add(&lmb, gd->ram_base, gd->ram_size);
 525         boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
 526         size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
 527         reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
 528
 529         if (!reg)
 530                 reg = gd->ram_top - size;
 531
 532         return reg + size;
 533 }
 534 #else
 535 int dram_init_banksize(void)
 536 {
 537         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 538         gd->bd->bi_dram[0].size = get_effective_memsize();
 539
 540         mem_map_fill();
 541
 542         return 0;
 543 }
 544
 545 int dram_init(void)
 546 {
 547         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 548                                     CONFIG_SYS_SDRAM_SIZE);
 549
 550         return 0;
 551 }
 552 #endif
 553
 554 #if !CONFIG_IS_ENABLED(SYSRESET)
 555 void reset_cpu(void)
 556 {
 557 }
 558 #endif
 559
 560 static u8 __maybe_unused zynqmp_get_bootmode(void)
 561 {
 562         u8 bootmode;
 563         u32 reg = 0;
 564         int ret;
 565
 566         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 567         if (ret)
 568                 return -EINVAL;
 569
 570         debug("HW boot mode: %x\n", reg & BOOT_MODES_MASK);
 571         debug("ALT boot mode: %x\n", reg >> BOOT_MODE_ALT_SHIFT);
 572
 573         if (reg >> BOOT_MODE_ALT_SHIFT)
 574                 reg >>= BOOT_MODE_ALT_SHIFT;
 575
 576         bootmode = reg & BOOT_MODES_MASK;
 577
 578         return bootmode;
 579 }
 580
 581 #if defined(CONFIG_BOARD_LATE_INIT)
 582 static const struct {
 583         u32 bit;
 584         const char *name;
 585 } reset_reasons[] = {
 586         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 587         { RESET_REASON_SOFT, "SOFT" },
 588         { RESET_REASON_SRST, "SRST" },
 589         { RESET_REASON_PSONLY, "PS-ONLY" },
 590         { RESET_REASON_PMU, "PMU" },
 591         { RESET_REASON_INTERNAL, "INTERNAL" },
 592         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 593         {}
 594 };
 595
 596 static int reset_reason(void)
 597 {
 598         u32 reg;
 599         int i, ret;
 600         const char *reason = NULL;
 601
 602         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 603         if (ret)
 604                 return -EINVAL;
 605
 606         puts("Reset reason:\t");
 607
 608         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 609                 if (reg & reset_reasons[i].bit) {
 610                         reason = reset_reasons[i].name;
 611                         printf("%s ", reset_reasons[i].name);
 612                         break;
 613                 }
 614         }
 615
 616         puts("\n");
 617
 618         env_set("reset_reason", reason);
 619
 620         return 0;
 621 }
 622
 623 static int set_fdtfile(void)
 624 {
 625         char *compatible, *fdtfile;
 626         const char *suffix = ".dtb";
 627         const char *vendor = "xilinx/";
 628         int fdt_compat_len;
 629
 630         if (env_get("fdtfile"))
 631                 return 0;
 632
 633         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
 634                                          &fdt_compat_len);
 635         if (compatible && fdt_compat_len) {
 636                 char *name;
 637
 638                 debug("Compatible: %s\n", compatible);
 639
 640                 name = strchr(compatible, ',');
 641                 if (!name)
 642                         return -EINVAL;
 643
 644                 name++;
 645
 646                 fdtfile = calloc(1, strlen(vendor) + strlen(name) +
 647                                  strlen(suffix) + 1);
 648                 if (!fdtfile)
 649                         return -ENOMEM;
 650
 651                 sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
 652
 653                 env_set("fdtfile", fdtfile);
 654                 free(fdtfile);
 655         }
 656
 657         return 0;
 658 }
 659
 660 int board_late_init(void)
 661 {
 662         u8 bootmode;
 663         struct udevice *dev;
 664         int bootseq = -1;
 665         int bootseq_len = 0;
 666         int env_targets_len = 0;
 667         const char *mode;
 668         char *new_targets;
 669         char *env_targets;
 670         int ret, multiboot;
 671
 672 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 673         usb_ether_init();
 674 #endif
 675
 676         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 677                 debug("Saved variables - Skipping\n");
 678                 return 0;
 679         }
 680
 681         if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
 682                 return 0;
 683
 684         ret = set_fdtfile();
 685         if (ret)
 686                 return ret;
 687
 688         multiboot = multi_boot();
 689         if (multiboot >= 0)
 690                 env_set_hex("multiboot", multiboot);
 691
 692         bootmode = zynqmp_get_bootmode();
 693
 694         puts("Bootmode: ");
 695         switch (bootmode) {
 696         case USB_MODE:
 697                 puts("USB_MODE\n");
 698                 mode = "usb_dfu0 usb_dfu1";
 699                 env_set("modeboot", "usb_dfu_spl");
 700                 break;
 701         case JTAG_MODE:
 702                 puts("JTAG_MODE\n");
 703                 mode = "jtag pxe dhcp";
 704                 env_set("modeboot", "jtagboot");
 705                 break;
 706         case QSPI_MODE_24BIT:
 707         case QSPI_MODE_32BIT:
 708                 mode = "qspi0";
 709                 puts("QSPI_MODE\n");
 710                 env_set("modeboot", "qspiboot");
 711                 break;
 712         case EMMC_MODE:
 713                 puts("EMMC_MODE\n");
 714                 if (uclass_get_device_by_name(UCLASS_MMC,
 715                                               "mmc@ff160000", &dev) &&
 716                     uclass_get_device_by_name(UCLASS_MMC,
 717                                               "sdhci@ff160000", &dev)) {
 718                         puts("Boot from EMMC but without SD0 enabled!\n");
 719                         return -1;
 720                 }
 721                 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
 722
 723                 mode = "mmc";
 724                 bootseq = dev_seq(dev);
 725                 env_set("modeboot", "emmcboot");
 726                 break;
 727         case SD_MODE:
 728                 puts("SD_MODE\n");
 729                 if (uclass_get_device_by_name(UCLASS_MMC,
 730                                               "mmc@ff160000", &dev) &&
 731                     uclass_get_device_by_name(UCLASS_MMC,
 732                                               "sdhci@ff160000", &dev)) {
 733                         puts("Boot from SD0 but without SD0 enabled!\n");
 734                         return -1;
 735                 }
 736                 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
 737
 738                 mode = "mmc";
 739                 bootseq = dev_seq(dev);
 740                 env_set("modeboot", "sdboot");
 741                 break;
 742         case SD1_LSHFT_MODE:
 743                 puts("LVL_SHFT_");
 744                 fallthrough;
 745         case SD_MODE1:
 746                 puts("SD_MODE1\n");
 747                 if (uclass_get_device_by_name(UCLASS_MMC,
 748                                               "mmc@ff170000", &dev) &&
 749                     uclass_get_device_by_name(UCLASS_MMC,
 750                                               "sdhci@ff170000", &dev)) {
 751                         puts("Boot from SD1 but without SD1 enabled!\n");
 752                         return -1;
 753                 }
 754                 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
 755
 756                 mode = "mmc";
 757                 bootseq = dev_seq(dev);
 758                 env_set("modeboot", "sdboot");
 759                 break;
 760         case NAND_MODE:
 761                 puts("NAND_MODE\n");
 762                 mode = "nand0";
 763                 env_set("modeboot", "nandboot");
 764                 break;
 765         default:
 766                 mode = "";
 767                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 768                 break;
 769         }
 770
 771         if (bootseq >= 0) {
 772                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 773                 debug("Bootseq len: %x\n", bootseq_len);
 774                 env_set_hex("bootseq", bootseq);
 775         }
 776
 777         /*
 778          * One terminating char + one byte for space between mode
 779          * and default boot_targets
 780          */
 781         env_targets = env_get("boot_targets");
 782         if (env_targets)
 783                 env_targets_len = strlen(env_targets);
 784
 785         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 786                              bootseq_len);
 787         if (!new_targets)
 788                 return -ENOMEM;
 789
 790         if (bootseq >= 0)
 791                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 792                         env_targets ? env_targets : "");
 793         else
 794                 sprintf(new_targets, "%s %s", mode,
 795                         env_targets ? env_targets : "");
 796
 797         env_set("boot_targets", new_targets);
 798         free(new_targets);
 799
 800         reset_reason();
 801
 802         return board_late_init_xilinx();
 803 }
 804 #endif
 805
 806 int checkboard(void)
 807 {
 808         puts("Board: Xilinx ZynqMP\n");
 809         return 0;
 810 }
 811
 812 int mmc_get_env_dev(void)
 813 {
 814         struct udevice *dev;
 815         int bootseq = 0;
 816
 817         switch (zynqmp_get_bootmode()) {
 818         case EMMC_MODE:
 819         case SD_MODE:
 820                 if (uclass_get_device_by_name(UCLASS_MMC,
 821                                               "mmc@ff160000", &dev) &&
 822                     uclass_get_device_by_name(UCLASS_MMC,
 823                                               "sdhci@ff160000", &dev)) {
 824                         return -1;
 825                 }
 826                 bootseq = dev_seq(dev);
 827                 break;
 828         case SD1_LSHFT_MODE:
 829         case SD_MODE1:
 830                 if (uclass_get_device_by_name(UCLASS_MMC,
 831                                               "mmc@ff170000", &dev) &&
 832                     uclass_get_device_by_name(UCLASS_MMC,
 833                                               "sdhci@ff170000", &dev)) {
 834                         return -1;
 835                 }
 836                 bootseq = dev_seq(dev);
 837                 break;
 838         default:
 839                 break;
 840         }
 841
 842         debug("bootseq %d\n", bootseq);
 843
 844         return bootseq;
 845 }
 846
 847 enum env_location env_get_location(enum env_operation op, int prio)
 848 {
 849         u32 bootmode = zynqmp_get_bootmode();
 850
 851         if (prio)
 852                 return ENVL_UNKNOWN;
 853
 854         switch (bootmode) {
 855         case EMMC_MODE:
 856         case SD_MODE:
 857         case SD1_LSHFT_MODE:
 858         case SD_MODE1:
 859                 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
 860                         return ENVL_FAT;
 861                 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
 862                         return ENVL_EXT4;
 863                 return ENVL_NOWHERE;
 864         case NAND_MODE:
 865                 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
 866                         return ENVL_NAND;
 867                 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
 868                         return ENVL_UBI;
 869                 return ENVL_NOWHERE;
 870         case QSPI_MODE_24BIT:
 871         case QSPI_MODE_32BIT:
 872                 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
 873                         return ENVL_SPI_FLASH;
 874                 return ENVL_NOWHERE;
 875         case JTAG_MODE:
 876         default:
 877                 return ENVL_NOWHERE;
 878         }
 879 }
 880
 881 #if defined(CONFIG_SET_DFU_ALT_INFO)
 882
 883 #define DFU_ALT_BUF_LEN         SZ_1K
 884
 885 void set_dfu_alt_info(char *interface, char *devstr)
 886 {
 887         u8 multiboot;
 888         int bootseq = 0;
 889
 890         ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
 891
 892         if (!CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) &&
 893             env_get("dfu_alt_info"))
 894                 return;
 895
 896         memset(buf, 0, sizeof(buf));
 897
 898         multiboot = multi_boot();
 899         if (multiboot < 0)
 900                 multiboot = 0;
 901
 902         multiboot = env_get_hex("multiboot", multiboot);
 903         debug("Multiboot: %d\n", multiboot);
 904
 905         switch (zynqmp_get_bootmode()) {
 906         case EMMC_MODE:
 907         case SD_MODE:
 908         case SD1_LSHFT_MODE:
 909         case SD_MODE1:
 910                 bootseq = mmc_get_env_dev();
 911                 if (!multiboot)
 912                         snprintf(buf, DFU_ALT_BUF_LEN,
 913                                  "mmc %d:1=boot.bin fat %d 1;"
 914                                  "%s fat %d 1",
 915                                  bootseq, bootseq,
 916                                  CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
 917                 else
 918                         snprintf(buf, DFU_ALT_BUF_LEN,
 919                                  "mmc %d:1=boot%04d.bin fat %d 1;"
 920                                  "%s fat %d 1",
 921                                  bootseq, multiboot, bootseq,
 922                                  CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
 923                 break;
 924         case QSPI_MODE_24BIT:
 925         case QSPI_MODE_32BIT:
 926                 snprintf(buf, DFU_ALT_BUF_LEN,
 927                          "sf 0:0=boot.bin raw %x 0x1500000;"
 928                          "%s raw 0x%x 0x500000",
 929                          multiboot * SZ_32K, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
 930                          CONFIG_SYS_SPI_U_BOOT_OFFS);
 931                 break;
 932         default:
 933                 return;
 934         }
 935
 936         env_set("dfu_alt_info", buf);
 937         puts("DFU alt info setting: done\n");
 938 }
 939 #endif