board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <sata.h>
  10 #include <ahci.h>
  11 #include <scsi.h>
  12 #include <malloc.h>
  13 #include <wdt.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/arch/psu_init_gpl.h>
  18 #include <asm/io.h>
  19 #include <dm/device.h>
  20 #include <dm/uclass.h>
  21 #include <usb.h>
  22 #include <dwc3-uboot.h>
  23 #include <zynqmppl.h>
  24 #include <g_dnl.h>
  25 #include <linux/sizes.h>
  26
  27 #include "pm_cfg_obj.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  32     !defined(CONFIG_SPL_BUILD)
  33 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  34
  35 static const struct {
  36         u32 id;
  37         u32 ver;
  38         char *name;
  39         bool evexists;
  40 } zynqmp_devices[] = {
  41         {
  42                 .id = 0x10,
  43                 .name = "3eg",
  44         },
  45         {
  46                 .id = 0x10,
  47                 .ver = 0x2c,
  48                 .name = "3cg",
  49         },
  50         {
  51                 .id = 0x11,
  52                 .name = "2eg",
  53         },
  54         {
  55                 .id = 0x11,
  56                 .ver = 0x2c,
  57                 .name = "2cg",
  58         },
  59         {
  60                 .id = 0x20,
  61                 .name = "5ev",
  62                 .evexists = 1,
  63         },
  64         {
  65                 .id = 0x20,
  66                 .ver = 0x100,
  67                 .name = "5eg",
  68                 .evexists = 1,
  69         },
  70         {
  71                 .id = 0x20,
  72                 .ver = 0x12c,
  73                 .name = "5cg",
  74                 .evexists = 1,
  75         },
  76         {
  77                 .id = 0x21,
  78                 .name = "4ev",
  79                 .evexists = 1,
  80         },
  81         {
  82                 .id = 0x21,
  83                 .ver = 0x100,
  84                 .name = "4eg",
  85                 .evexists = 1,
  86         },
  87         {
  88                 .id = 0x21,
  89                 .ver = 0x12c,
  90                 .name = "4cg",
  91                 .evexists = 1,
  92         },
  93         {
  94                 .id = 0x30,
  95                 .name = "7ev",
  96                 .evexists = 1,
  97         },
  98         {
  99                 .id = 0x30,
 100                 .ver = 0x100,
 101                 .name = "7eg",
 102                 .evexists = 1,
 103         },
 104         {
 105                 .id = 0x30,
 106                 .ver = 0x12c,
 107                 .name = "7cg",
 108                 .evexists = 1,
 109         },
 110         {
 111                 .id = 0x38,
 112                 .name = "9eg",
 113         },
 114         {
 115                 .id = 0x38,
 116                 .ver = 0x2c,
 117                 .name = "9cg",
 118         },
 119         {
 120                 .id = 0x39,
 121                 .name = "6eg",
 122         },
 123         {
 124                 .id = 0x39,
 125                 .ver = 0x2c,
 126                 .name = "6cg",
 127         },
 128         {
 129                 .id = 0x40,
 130                 .name = "11eg",
 131         },
 132         { /* For testing purpose only */
 133                 .id = 0x50,
 134                 .ver = 0x2c,
 135                 .name = "15cg",
 136         },
 137         {
 138                 .id = 0x50,
 139                 .name = "15eg",
 140         },
 141         {
 142                 .id = 0x58,
 143                 .name = "19eg",
 144         },
 145         {
 146                 .id = 0x59,
 147                 .name = "17eg",
 148         },
 149         {
 150                 .id = 0x61,
 151                 .name = "21dr",
 152         },
 153         {
 154                 .id = 0x63,
 155                 .name = "23dr",
 156         },
 157         {
 158                 .id = 0x65,
 159                 .name = "25dr",
 160         },
 161         {
 162                 .id = 0x64,
 163                 .name = "27dr",
 164         },
 165         {
 166                 .id = 0x60,
 167                 .name = "28dr",
 168         },
 169         {
 170                 .id = 0x62,
 171                 .name = "29dr",
 172         },
 173         {
 174                 .id = 0x66,
 175                 .name = "39dr",
 176         },
 177 };
 178 #endif
 179
 180 int chip_id(unsigned char id)
 181 {
 182         struct pt_regs regs;
 183         int val = -EINVAL;
 184
 185         if (current_el() != 3) {
 186                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 187                 regs.regs[1] = 0;
 188                 regs.regs[2] = 0;
 189                 regs.regs[3] = 0;
 190
 191                 smc_call(&regs);
 192
 193                 /*
 194                  * SMC returns:
 195                  * regs[0][31:0]  = status of the operation
 196                  * regs[0][63:32] = CSU.IDCODE register
 197                  * regs[1][31:0]  = CSU.version register
 198                  * regs[1][63:32] = CSU.IDCODE2 register
 199                  */
 200                 switch (id) {
 201                 case IDCODE:
 202                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 203                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 204                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 205                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 206                         val = regs.regs[0];
 207                         break;
 208                 case VERSION:
 209                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 210                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 211                         val = regs.regs[1];
 212                         break;
 213                 case IDCODE2:
 214                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 215                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 216                         val = regs.regs[1];
 217                         break;
 218                 default:
 219                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 220                 }
 221         } else {
 222                 switch (id) {
 223                 case IDCODE:
 224                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 225                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 226                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 227                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 228                         break;
 229                 case VERSION:
 230                         val = readl(ZYNQMP_CSU_VER_ADDR);
 231                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 232                         break;
 233                 default:
 234                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 235                 }
 236         }
 237
 238         return val;
 239 }
 240
 241 #define ZYNQMP_VERSION_SIZE             9
 242 #define ZYNQMP_PL_STATUS_BIT            9
 243 #define ZYNQMP_IPDIS_VCU_BIT            8
 244 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 245 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 246 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 247                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 248 #define MAX_VARIANTS_EV                 3
 249
 250 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 251         !defined(CONFIG_SPL_BUILD)
 252 static char *zynqmp_get_silicon_idcode_name(void)
 253 {
 254         u32 i, id, ver, j;
 255         char *buf;
 256         static char name[ZYNQMP_VERSION_SIZE];
 257
 258         id = chip_id(IDCODE);
 259         ver = chip_id(IDCODE2);
 260
 261         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 262                 if (zynqmp_devices[i].id == id) {
 263                         if (zynqmp_devices[i].evexists &&
 264                             !(ver & ZYNQMP_PL_STATUS_MASK))
 265                                 break;
 266                         if (zynqmp_devices[i].ver == (ver &
 267                             ZYNQMP_CSU_VERSION_MASK))
 268                                 break;
 269                 }
 270         }
 271
 272         if (i >= ARRAY_SIZE(zynqmp_devices))
 273                 return "unknown";
 274
 275         strncat(name, "zu", 2);
 276         if (!zynqmp_devices[i].evexists ||
 277             (ver & ZYNQMP_PL_STATUS_MASK)) {
 278                 strncat(name, zynqmp_devices[i].name,
 279                         ZYNQMP_VERSION_SIZE - 3);
 280                 return name;
 281         }
 282
 283         /*
 284          * Here we are means, PL not powered up and ev variant
 285          * exists. So, we need to ignore VCU disable bit(8) in
 286          * version and findout if its CG or EG/EV variant.
 287          */
 288         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 289                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 290                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 291                         strncat(name, zynqmp_devices[i].name,
 292                                 ZYNQMP_VERSION_SIZE - 3);
 293                         break;
 294                 }
 295         }
 296
 297         if (j >= MAX_VARIANTS_EV)
 298                 return "unknown";
 299
 300         if (strstr(name, "eg") || strstr(name, "ev")) {
 301                 buf = strstr(name, "e");
 302                 *buf = '\0';
 303         }
 304
 305         return name;
 306 }
 307 #endif
 308
 309 int board_early_init_f(void)
 310 {
 311         int ret = 0;
 312 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 313         u32 pm_api_version;
 314
 315         pm_api_version = zynqmp_pmufw_version();
 316         printf("PMUFW:\tv%d.%d\n",
 317                pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
 318                pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
 319
 320         if (pm_api_version < ZYNQMP_PM_VERSION)
 321                 panic("PMUFW version error. Expected: v%d.%d\n",
 322                       ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
 323 #endif
 324
 325 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 326         ret = psu_init();
 327 #endif
 328
 329         return ret;
 330 }
 331
 332 int board_init(void)
 333 {
 334 #if defined(CONFIG_SPL_BUILD)
 335         /* Check *at build time* if the filename is an non-empty string */
 336         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 337                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 338                                                 zynqmp_pm_cfg_obj_size);
 339 #endif
 340
 341         printf("EL Level:\tEL%d\n", current_el());
 342
 343 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 344     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 345     defined(CONFIG_SPL_BUILD))
 346         if (current_el() != 3) {
 347                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 348                 printf("Chip ID:\t%s\n", zynqmppl.name);
 349                 fpga_init();
 350                 fpga_add(fpga_xilinx, &zynqmppl);
 351         }
 352 #endif
 353
 354         return 0;
 355 }
 356
 357 int board_early_init_r(void)
 358 {
 359         u32 val;
 360
 361         if (current_el() != 3)
 362                 return 0;
 363
 364         val = readl(&crlapb_base->timestamp_ref_ctrl);
 365         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 366
 367         if (!val) {
 368                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 369                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 370                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 371
 372                 /* Program freq register in System counter */
 373                 writel(zynqmp_get_system_timer_freq(),
 374                        &iou_scntr_secure->base_frequency_id_register);
 375                 /* And enable system counter */
 376                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 377                        &iou_scntr_secure->counter_control_register);
 378         }
 379         return 0;
 380 }
 381
 382 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 383                          char * const argv[])
 384 {
 385         int ret = 0;
 386
 387         if (current_el() > 1) {
 388                 smp_kick_all_cpus();
 389                 dcache_disable();
 390                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 391                                     ES_TO_AARCH64);
 392         } else {
 393                 printf("FAIL: current EL is not above EL1\n");
 394                 ret = EINVAL;
 395         }
 396         return ret;
 397 }
 398
 399 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 400 int dram_init_banksize(void)
 401 {
 402         int ret;
 403
 404         ret = fdtdec_setup_memory_banksize();
 405         if (ret)
 406                 return ret;
 407
 408         mem_map_fill();
 409
 410         return 0;
 411 }
 412
 413 int dram_init(void)
 414 {
 415         if (fdtdec_setup_mem_size_base() != 0)
 416                 return -EINVAL;
 417
 418         return 0;
 419 }
 420 #else
 421 int dram_init_banksize(void)
 422 {
 423 #if defined(CONFIG_NR_DRAM_BANKS)
 424         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 425         gd->bd->bi_dram[0].size = get_effective_memsize();
 426 #endif
 427
 428         mem_map_fill();
 429
 430         return 0;
 431 }
 432
 433 int dram_init(void)
 434 {
 435         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 436                                     CONFIG_SYS_SDRAM_SIZE);
 437
 438         return 0;
 439 }
 440 #endif
 441
 442 void reset_cpu(ulong addr)
 443 {
 444 }
 445
 446 #if defined(CONFIG_BOARD_LATE_INIT)
 447 static const struct {
 448         u32 bit;
 449         const char *name;
 450 } reset_reasons[] = {
 451         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 452         { RESET_REASON_SOFT, "SOFT" },
 453         { RESET_REASON_SRST, "SRST" },
 454         { RESET_REASON_PSONLY, "PS-ONLY" },
 455         { RESET_REASON_PMU, "PMU" },
 456         { RESET_REASON_INTERNAL, "INTERNAL" },
 457         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 458         {}
 459 };
 460
 461 static int reset_reason(void)
 462 {
 463         u32 reg;
 464         int i, ret;
 465         const char *reason = NULL;
 466
 467         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 468         if (ret)
 469                 return -EINVAL;
 470
 471         puts("Reset reason:\t");
 472
 473         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 474                 if (reg & reset_reasons[i].bit) {
 475                         reason = reset_reasons[i].name;
 476                         printf("%s ", reset_reasons[i].name);
 477                         break;
 478                 }
 479         }
 480
 481         puts("\n");
 482
 483         env_set("reset_reason", reason);
 484
 485         ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
 486         if (ret)
 487                 return -EINVAL;
 488
 489         return ret;
 490 }
 491
 492 static int set_fdtfile(void)
 493 {
 494         char *compatible, *fdtfile;
 495         const char *suffix = ".dtb";
 496         const char *vendor = "xilinx/";
 497
 498         if (env_get("fdtfile"))
 499                 return 0;
 500
 501         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 502         if (compatible) {
 503                 debug("Compatible: %s\n", compatible);
 504
 505                 /* Discard vendor prefix */
 506                 strsep(&compatible, ",");
 507
 508                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 509                                  strlen(suffix) + 1);
 510                 if (!fdtfile)
 511                         return -ENOMEM;
 512
 513                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 514
 515                 env_set("fdtfile", fdtfile);
 516                 free(fdtfile);
 517         }
 518
 519         return 0;
 520 }
 521
 522 int board_late_init(void)
 523 {
 524         u32 reg = 0;
 525         u8 bootmode;
 526         struct udevice *dev;
 527         int bootseq = -1;
 528         int bootseq_len = 0;
 529         int env_targets_len = 0;
 530         const char *mode;
 531         char *new_targets;
 532         char *env_targets;
 533         int ret;
 534         ulong initrd_hi;
 535
 536 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 537         usb_ether_init();
 538 #endif
 539
 540         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 541                 debug("Saved variables - Skipping\n");
 542                 return 0;
 543         }
 544
 545         ret = set_fdtfile();
 546         if (ret)
 547                 return ret;
 548
 549         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 550         if (ret)
 551                 return -EINVAL;
 552
 553         if (reg >> BOOT_MODE_ALT_SHIFT)
 554                 reg >>= BOOT_MODE_ALT_SHIFT;
 555
 556         bootmode = reg & BOOT_MODES_MASK;
 557
 558         puts("Bootmode: ");
 559         switch (bootmode) {
 560         case USB_MODE:
 561                 puts("USB_MODE\n");
 562                 mode = "usb";
 563                 env_set("modeboot", "usb_dfu_spl");
 564                 break;
 565         case JTAG_MODE:
 566                 puts("JTAG_MODE\n");
 567                 mode = "pxe dhcp";
 568                 env_set("modeboot", "jtagboot");
 569                 break;
 570         case QSPI_MODE_24BIT:
 571         case QSPI_MODE_32BIT:
 572                 mode = "qspi0";
 573                 puts("QSPI_MODE\n");
 574                 env_set("modeboot", "qspiboot");
 575                 break;
 576         case EMMC_MODE:
 577                 puts("EMMC_MODE\n");
 578                 mode = "mmc0";
 579                 env_set("modeboot", "emmcboot");
 580                 break;
 581         case SD_MODE:
 582                 puts("SD_MODE\n");
 583                 if (uclass_get_device_by_name(UCLASS_MMC,
 584                                               "mmc@ff160000", &dev) &&
 585                     uclass_get_device_by_name(UCLASS_MMC,
 586                                               "sdhci@ff160000", &dev)) {
 587                         puts("Boot from SD0 but without SD0 enabled!\n");
 588                         return -1;
 589                 }
 590                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 591
 592                 mode = "mmc";
 593                 bootseq = dev->seq;
 594                 env_set("modeboot", "sdboot");
 595                 break;
 596         case SD1_LSHFT_MODE:
 597                 puts("LVL_SHFT_");
 598                 /* fall through */
 599         case SD_MODE1:
 600                 puts("SD_MODE1\n");
 601                 if (uclass_get_device_by_name(UCLASS_MMC,
 602                                               "mmc@ff170000", &dev) &&
 603                     uclass_get_device_by_name(UCLASS_MMC,
 604                                               "sdhci@ff170000", &dev)) {
 605                         puts("Boot from SD1 but without SD1 enabled!\n");
 606                         return -1;
 607                 }
 608                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 609
 610                 mode = "mmc";
 611                 bootseq = dev->seq;
 612                 env_set("modeboot", "sdboot");
 613                 break;
 614         case NAND_MODE:
 615                 puts("NAND_MODE\n");
 616                 mode = "nand0";
 617                 env_set("modeboot", "nandboot");
 618                 break;
 619         default:
 620                 mode = "";
 621                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 622                 break;
 623         }
 624
 625         if (bootseq >= 0) {
 626                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 627                 debug("Bootseq len: %x\n", bootseq_len);
 628         }
 629
 630         /*
 631          * One terminating char + one byte for space between mode
 632          * and default boot_targets
 633          */
 634         env_targets = env_get("boot_targets");
 635         if (env_targets)
 636                 env_targets_len = strlen(env_targets);
 637
 638         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 639                              bootseq_len);
 640         if (!new_targets)
 641                 return -ENOMEM;
 642
 643         if (bootseq >= 0)
 644                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 645                         env_targets ? env_targets : "");
 646         else
 647                 sprintf(new_targets, "%s %s", mode,
 648                         env_targets ? env_targets : "");
 649
 650         env_set("boot_targets", new_targets);
 651
 652         initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
 653         initrd_hi = round_down(initrd_hi, SZ_16M);
 654         env_set_addr("initrd_high", (void *)initrd_hi);
 655
 656         reset_reason();
 657
 658         return 0;
 659 }
 660 #endif
 661
 662 int checkboard(void)
 663 {
 664         puts("Board: Xilinx ZynqMP\n");
 665         return 0;
 666 }