board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
   4  */
   5
   6 #include <asm/arch/psu_init_gpl.h>
   7 #include <xil_io.h>
   8
   9 static unsigned long psu_pll_init_data(void)
  10 {
  11         psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
  12         psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014000U);
  13         psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
  14         psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
  15         psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
  16         mask_poll(0xFF5E0040, 0x00000002U);
  17         psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
  18         psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
  19         psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
  20         psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
  21         psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
  22         psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
  23         psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
  24         psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
  25         psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
  26         mask_poll(0xFF5E0040, 0x00000001U);
  27         psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
  28         psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
  29         psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
  30         psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
  31         psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
  32         psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
  33         psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
  34         psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
  35         mask_poll(0xFD1A0044, 0x00000001U);
  36         psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
  37         psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
  38         psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
  39         psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
  40         psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
  41         psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
  42         psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
  43         psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
  44         mask_poll(0xFD1A0044, 0x00000002U);
  45         psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
  46         psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
  47         psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
  48         psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
  49         psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U);
  50         psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
  51         psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
  52         psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
  53         mask_poll(0xFD1A0044, 0x00000004U);
  54         psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
  55         psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U);
  56         psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
  57
  58         return 1;
  59 }
  60
  61 static unsigned long psu_clock_init_data(void)
  62 {
  63         psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U);
  64         psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U);
  65         psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U);
  66         psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
  67         psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
  68         psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
  69         psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
  70         psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
  71         psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
  72         psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
  73         psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
  74         psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
  75         psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
  76         psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
  77         psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
  78         psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000400U);
  79         psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
  80         psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000200U);
  81         psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
  82         psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
  83         psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000200U);
  84         psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010B02U);
  85         psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
  86         psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
  87         psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
  88         psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
  89         psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
  90         psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
  91         psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
  92         psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
  93         psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U);
  94         psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
  95         psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
  96         psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
  97         psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
  98         psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
  99         psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
 100         psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
 101
 102         return 1;
 103 }
 104
 105 static unsigned long psu_ddr_init_data(void)
 106 {
 107         psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
 108         psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U);
 109         psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
 110         psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U);
 111         psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U);
 112         psu_mask_write(0xFD070030, 0x0000007FU, 0x00000008U);
 113         psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
 114         psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
 115         psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
 116         psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
 117         psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U);
 118         psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
 119         psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
 120         psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
 121         psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
 122         psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U);
 123         psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
 124         psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
 125         psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U);
 126         psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
 127         psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
 128         psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
 129         psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
 130         psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
 131         psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
 132         psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U);
 133         psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U);
 134         psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1310U);
 135         psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U);
 136         psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU);
 137         psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U);
 138         psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U);
 139         psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U);
 140         psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U);
 141         psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
 142         psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
 143         psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
 144         psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U);
 145         psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U);
 146         psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU);
 147         psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
 148         psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
 149         psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
 150         psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U);
 151         psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
 152         psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
 153         psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U);
 154         psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
 155         psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
 156         psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
 157         psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
 158         psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
 159         psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
 160         psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
 161         psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U);
 162         psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
 163         psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
 164         psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
 165         psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
 166         psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
 167         psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
 168         psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
 169         psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
 170         psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
 171         psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
 172         psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
 173         psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
 174         psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
 175         psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
 176         psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
 177         psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
 178         psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
 179         psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
 180         psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
 181         psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
 182         psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
 183         psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
 184         psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
 185         psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
 186         psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
 187         psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
 188         psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
 189         psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
 190         psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
 191         psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
 192         psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
 193         psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
 194         psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
 195         psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
 196         psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
 197         psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
 198         psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
 199         psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
 200         psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
 201         psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
 202         psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
 203         psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
 204         psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
 205         psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
 206         psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
 207         psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
 208         psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
 209         psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
 210         psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
 211         psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
 212         psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
 213         psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
 214         psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
 215         psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
 216         psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
 217         psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
 218         psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
 219         psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
 220         psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
 221         psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
 222         psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
 223         psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
 224         psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
 225         psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U);
 226         psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
 227         psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
 228         psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
 229         psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
 230         psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
 231         psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
 232         psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
 233         psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU);
 234         psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
 235         psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U);
 236         psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0510U);
 237         psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U);
 238         psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
 239         psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU);
 240         psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU);
 241         psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U);
 242         psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
 243         psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
 244         psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
 245         psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
 246         psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
 247         psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U);
 248         psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U);
 249         psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
 250         psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
 251         psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
 252         psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
 253         psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
 254         psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000021U);
 255         psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
 256         psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
 257         psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
 258         psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
 259         psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
 260         psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
 261         psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
 262         psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
 263         psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
 264         psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
 265         psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
 266         psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
 267         psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
 268         psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
 269         psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
 270         psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
 271         psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
 272         psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
 273         psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
 274         psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
 275         psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
 276         psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
 277         psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U);
 278         psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
 279         psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
 280         psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
 281         psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
 282         psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
 283         psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
 284         psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
 285         psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
 286         psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
 287         psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
 288         psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
 289         psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
 290         psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
 291         psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
 292         psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
 293         psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
 294         psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
 295         psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
 296         psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
 297         psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F50CU);
 298         psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
 299         psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
 300         psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
 301         psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
 302         psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
 303         psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F50CU);
 304         psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
 305         psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
 306         psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U);
 307         psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U);
 308         psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU);
 309         psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0129A4A4U);
 310         psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U);
 311         psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
 312         psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
 313         psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U);
 314         psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U);
 315         psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU);
 316         psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U);
 317         psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U);
 318         psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
 319         psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
 320         psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U);
 321         psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U);
 322         psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU);
 323         psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U);
 324         psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U);
 325         psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
 326         psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
 327         psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U);
 328         psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U);
 329         psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU);
 330         psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U);
 331         psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U);
 332         psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
 333         psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
 334         psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
 335         psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
 336         psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
 337         psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
 338         psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U);
 339         psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
 340         psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
 341         psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
 342         psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
 343         psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
 344         psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
 345         psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
 346         psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
 347         psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
 348         psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
 349         psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
 350         psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
 351         psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU);
 352         psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U);
 353         psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U);
 354         psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
 355         psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U);
 356         psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU);
 357         psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U);
 358         psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U);
 359         psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
 360         psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U);
 361         psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
 362         psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
 363         psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
 364         psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
 365         psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
 366         psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
 367         psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
 368
 369         return 1;
 370 }
 371
 372 static unsigned long psu_ddr_qos_init_data(void)
 373 {
 374         return 1;
 375 }
 376
 377 static unsigned long psu_mio_init_data(void)
 378 {
 379         psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
 380         psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
 381         psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
 382         psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
 383         psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
 384         psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
 385         psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
 386         psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
 387         psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
 388         psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
 389         psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
 390         psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U);
 391         psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U);
 392         psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U);
 393         psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U);
 394         psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U);
 395         psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U);
 396         psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
 397         psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
 398         psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
 399         psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
 400         psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
 401         psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
 402         psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
 403         psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
 404         psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
 405         psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
 406         psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
 407         psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
 408         psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
 409         psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
 410         psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
 411         psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
 412         psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
 413         psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
 414         psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
 415         psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
 416         psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
 417         psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
 418         psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
 419         psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
 420         psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
 421         psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
 422         psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
 423         psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
 424         psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
 425         psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
 426         psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
 427         psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
 428         psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
 429         psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U);
 430         psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U);
 431         psu_mask_write(0xFF180204, 0x00FFE000U, 0x00000000U);
 432         psu_mask_write(0xFF180208, 0xFFFFE3FCU, 0x00B02240U);
 433         psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
 434         psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
 435         psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
 436         psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
 437         psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
 438         psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
 439         psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
 440         psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
 441         psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
 442         psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
 443         psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
 444         psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
 445         psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
 446         psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
 447         psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
 448         psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
 449         psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
 450         psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
 451         psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
 452         psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
 453
 454         return 1;
 455 }
 456
 457 static unsigned long psu_peripherals_pre_init_data(void)
 458 {
 459         psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
 460
 461         return 1;
 462 }
 463
 464 static unsigned long psu_peripherals_init_data(void)
 465 {
 466         psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U);
 467         psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
 468         psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
 469         psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
 470         psu_mask_write(0xFF5E023C, 0x00000C00U, 0x00000000U);
 471         psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
 472         psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
 473         psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
 474         psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
 475         psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
 476         psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
 477         psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
 478         psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
 479         psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
 480         psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
 481         psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
 482         psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
 483         psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
 484         psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
 485         psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
 486         psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
 487         psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
 488         psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
 489         psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
 490         psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 491         psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 492         psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
 493         psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
 494         psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
 495         psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
 496         psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
 497         psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
 498
 499         mask_delay(1);
 500         psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
 501
 502         mask_delay(5);
 503         psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
 504
 505         return 1;
 506 }
 507
 508 static unsigned long psu_serdes_init_data(void)
 509 {
 510         psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
 511         psu_mask_write(0xFD410004, 0x0000001FU, 0x00000008U);
 512         psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
 513         psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U);
 514         psu_mask_write(0xFD406094, 0x00000010U, 0x00000010U);
 515         psu_mask_write(0xFD406368, 0x000000FFU, 0x00000038U);
 516         psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
 517         psu_mask_write(0xFD406370, 0x000000FFU, 0x000000F4U);
 518         psu_mask_write(0xFD406374, 0x000000FFU, 0x00000031U);
 519         psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
 520         psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
 521         psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
 522         psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
 523         psu_mask_write(0xFD40506C, 0x00000003U, 0x00000003U);
 524         psu_mask_write(0xFD4040F4, 0x00000003U, 0x00000003U);
 525         psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
 526         psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
 527         psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
 528         psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
 529         psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
 530         psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
 531         psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
 532         psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
 533         psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U);
 534         psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U);
 535         psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U);
 536         psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
 537         psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
 538         psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
 539         psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU);
 540         psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
 541         psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU);
 542         psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
 543         psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
 544         psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
 545         psu_mask_write(0xFD4058F8, 0x000000FFU, 0x0000001AU);
 546         psu_mask_write(0xFD4058FC, 0x000000FFU, 0x0000001AU);
 547         psu_mask_write(0xFD405990, 0x000000FFU, 0x00000010U);
 548         psu_mask_write(0xFD405924, 0x000000FFU, 0x000000FEU);
 549         psu_mask_write(0xFD405928, 0x000000FFU, 0x00000000U);
 550         psu_mask_write(0xFD405900, 0x000000FFU, 0x0000001AU);
 551         psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
 552         psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
 553         psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
 554         psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
 555         psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
 556         psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
 557         psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
 558         psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
 559         psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
 560         psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
 561         psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
 562         psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
 563         psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
 564         psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
 565         psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
 566         psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
 567         psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
 568         psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
 569         psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
 570         psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
 571         psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
 572         psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
 573         psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
 574         psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
 575         psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
 576         psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
 577         psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
 578         psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
 579         psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
 580         psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
 581         psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
 582         psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
 583         psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
 584         psu_mask_write(0xFD410010, 0x00000077U, 0x00000035U);
 585         psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
 586         psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
 587
 588         return 1;
 589 }
 590
 591 static unsigned long psu_resetout_init_data(void)
 592 {
 593         psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
 594         psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
 595         psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
 596         psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
 597         psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
 598         psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
 599         psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
 600         psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
 601         psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
 602         psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
 603         psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
 604         psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
 605         psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
 606         psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
 607         psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
 608         psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
 609         psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
 610         psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
 611         mask_poll(0xFD4023E4, 0x00000010U);
 612         mask_poll(0xFD4063E4, 0x00000010U);
 613
 614         return 1;
 615 }
 616
 617 static unsigned long psu_resetin_init_data(void)
 618 {
 619         psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
 620         psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
 621         psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U);
 622
 623         return 1;
 624 }
 625
 626 static unsigned long psu_afi_config(void)
 627 {
 628         psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
 629         psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
 630         psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
 631
 632         return 1;
 633 }
 634
 635 static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt,
 636                       int d_lfhf, int d_cp, int d_res)
 637 {
 638         unsigned int pll_ctrl_regval;
 639         unsigned int pll_status_regval;
 640
 641         pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
 642         pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U);
 643         pll_ctrl_regval = pll_ctrl_regval | (1 << 16);
 644         Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
 645
 646         pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
 647         pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U);
 648         pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25);
 649         Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
 650
 651         pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
 652         pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U);
 653         pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13);
 654         Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
 655
 656         pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
 657         pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U);
 658         pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10);
 659         Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
 660
 661         pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
 662         pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U);
 663         pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5);
 664         Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
 665
 666         pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
 667         pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU);
 668         pll_ctrl_regval = pll_ctrl_regval | (d_res << 0);
 669         Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
 670
 671         pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
 672         pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U);
 673         pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8);
 674         Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
 675
 676         pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
 677         pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
 678         pll_ctrl_regval = pll_ctrl_regval | (1 << 3);
 679         Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
 680
 681         pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
 682         pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
 683         pll_ctrl_regval = pll_ctrl_regval | (1 << 0);
 684         Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
 685
 686         pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
 687         pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
 688         pll_ctrl_regval = pll_ctrl_regval | (0 << 0);
 689         Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
 690
 691         pll_status_regval = 0x00000000;
 692         while ((pll_status_regval & 0x00000002U) != 0x00000002U)
 693                 pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044));
 694
 695         pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
 696         pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
 697         pll_ctrl_regval = pll_ctrl_regval | (0 << 3);
 698         Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
 699 }
 700
 701 static unsigned long psu_ddr_phybringup_data(void)
 702 {
 703         unsigned int regval = 0;
 704
 705         for (int tp = 0; tp < 20; tp++)
 706                 regval = Xil_In32(0xFD070018);
 707         int cur_PLLCR0;
 708
 709         cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U;
 710         int cur_DX8SL0PLLCR0;
 711
 712         cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U;
 713         int cur_DX8SL1PLLCR0;
 714
 715         cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U;
 716         int cur_DX8SL2PLLCR0;
 717
 718         cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U;
 719         int cur_DX8SL3PLLCR0;
 720
 721         cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U;
 722         int cur_DX8SL4PLLCR0;
 723
 724         cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U;
 725         int cur_DX8SLBPLLCR0;
 726
 727         cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U;
 728         Xil_Out32(0xFD080068, 0x02120000);
 729         Xil_Out32(0xFD081404, 0x02120000);
 730         Xil_Out32(0xFD081444, 0x02120000);
 731         Xil_Out32(0xFD081484, 0x02120000);
 732         Xil_Out32(0xFD0814C4, 0x02120000);
 733         Xil_Out32(0xFD081504, 0x02120000);
 734         Xil_Out32(0xFD0817C4, 0x02120000);
 735         int cur_fbdiv;
 736
 737         cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U;
 738         dpll_prog(48, 63, 625, 3, 3, 2);
 739         for (int tp = 0; tp < 20; tp++)
 740                 regval = Xil_In32(0xFD070018);
 741         unsigned int pll_retry = 10;
 742         unsigned int pll_locked = 0;
 743
 744         while ((pll_retry > 0) && (!pll_locked)) {
 745                 Xil_Out32(0xFD080004, 0x00040010);
 746                 Xil_Out32(0xFD080004, 0x00040011);
 747
 748                 while ((Xil_In32(0xFD080030) & 0x1) != 1)
 749                         ;
 750                 pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
 751                     >> 31;
 752                 pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
 753                     >> 16;
 754                 pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
 755                     >> 16;
 756                 pll_retry--;
 757         }
 758         Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
 759         if (!pll_locked)
 760                 return (0);
 761
 762         Xil_Out32(0xFD080004U, 0x00040063U);
 763
 764         while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
 765                 ;
 766         prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
 767
 768         while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
 769                 ;
 770         Xil_Out32(0xFD070010U, 0x80000018U);
 771         Xil_Out32(0xFD0701B0U, 0x00000005U);
 772         regval = Xil_In32(0xFD070018);
 773         while ((regval & 0x1) != 0x0)
 774                 regval = Xil_In32(0xFD070018);
 775
 776         regval = Xil_In32(0xFD070018);
 777         regval = Xil_In32(0xFD070018);
 778         regval = Xil_In32(0xFD070018);
 779         regval = Xil_In32(0xFD070018);
 780         regval = Xil_In32(0xFD070018);
 781         regval = Xil_In32(0xFD070018);
 782         regval = Xil_In32(0xFD070018);
 783         regval = Xil_In32(0xFD070018);
 784         regval = Xil_In32(0xFD070018);
 785         regval = Xil_In32(0xFD070018);
 786         Xil_Out32(0xFD070014U, 0x00000331U);
 787         Xil_Out32(0xFD070010U, 0x80000018U);
 788         regval = Xil_In32(0xFD070018);
 789         while ((regval & 0x1) != 0x0)
 790                 regval = Xil_In32(0xFD070018);
 791
 792         regval = Xil_In32(0xFD070018);
 793         regval = Xil_In32(0xFD070018);
 794         regval = Xil_In32(0xFD070018);
 795         regval = Xil_In32(0xFD070018);
 796         regval = Xil_In32(0xFD070018);
 797         regval = Xil_In32(0xFD070018);
 798         regval = Xil_In32(0xFD070018);
 799         regval = Xil_In32(0xFD070018);
 800         regval = Xil_In32(0xFD070018);
 801         regval = Xil_In32(0xFD070018);
 802         Xil_Out32(0xFD070014U, 0x00000B36U);
 803         Xil_Out32(0xFD070010U, 0x80000018U);
 804         regval = Xil_In32(0xFD070018);
 805         while ((regval & 0x1) != 0x0)
 806                 regval = Xil_In32(0xFD070018);
 807
 808         regval = Xil_In32(0xFD070018);
 809         regval = Xil_In32(0xFD070018);
 810         regval = Xil_In32(0xFD070018);
 811         regval = Xil_In32(0xFD070018);
 812         regval = Xil_In32(0xFD070018);
 813         regval = Xil_In32(0xFD070018);
 814         regval = Xil_In32(0xFD070018);
 815         regval = Xil_In32(0xFD070018);
 816         regval = Xil_In32(0xFD070018);
 817         regval = Xil_In32(0xFD070018);
 818         Xil_Out32(0xFD070014U, 0x00000C21U);
 819         Xil_Out32(0xFD070010U, 0x80000018U);
 820         regval = Xil_In32(0xFD070018);
 821         while ((regval & 0x1) != 0x0)
 822                 regval = Xil_In32(0xFD070018);
 823
 824         regval = Xil_In32(0xFD070018);
 825         regval = Xil_In32(0xFD070018);
 826         regval = Xil_In32(0xFD070018);
 827         regval = Xil_In32(0xFD070018);
 828         regval = Xil_In32(0xFD070018);
 829         regval = Xil_In32(0xFD070018);
 830         regval = Xil_In32(0xFD070018);
 831         regval = Xil_In32(0xFD070018);
 832         regval = Xil_In32(0xFD070018);
 833         regval = Xil_In32(0xFD070018);
 834         Xil_Out32(0xFD070014U, 0x00000E19U);
 835         Xil_Out32(0xFD070010U, 0x80000018U);
 836         regval = Xil_In32(0xFD070018);
 837         while ((regval & 0x1) != 0x0)
 838                 regval = Xil_In32(0xFD070018);
 839
 840         regval = Xil_In32(0xFD070018);
 841         regval = Xil_In32(0xFD070018);
 842         regval = Xil_In32(0xFD070018);
 843         regval = Xil_In32(0xFD070018);
 844         regval = Xil_In32(0xFD070018);
 845         regval = Xil_In32(0xFD070018);
 846         regval = Xil_In32(0xFD070018);
 847         regval = Xil_In32(0xFD070018);
 848         regval = Xil_In32(0xFD070018);
 849         regval = Xil_In32(0xFD070018);
 850         Xil_Out32(0xFD070014U, 0x00001616U);
 851         Xil_Out32(0xFD070010U, 0x80000018U);
 852         Xil_Out32(0xFD070010U, 0x80000010U);
 853         Xil_Out32(0xFD0701B0U, 0x00000005U);
 854         Xil_Out32(0xFD070320U, 0x00000001U);
 855         while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
 856                 ;
 857         prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U);
 858         prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
 859         prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
 860         prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U);
 861         prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
 862         prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
 863         prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U);
 864         prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
 865         for (int tp = 0; tp < 20; tp++)
 866                 regval = Xil_In32(0xFD070018);
 867
 868         Xil_Out32(0xFD080068, cur_PLLCR0);
 869         Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0);
 870         Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0);
 871         Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0);
 872         Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0);
 873         Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0);
 874         Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0);
 875         for (int tp = 0; tp < 20; tp++)
 876                 regval = Xil_In32(0xFD070018);
 877
 878         dpll_prog(cur_fbdiv, 63, 625, 3, 3, 2);
 879         for (int tp = 0; tp < 2000; tp++)
 880                 regval = Xil_In32(0xFD070018);
 881
 882         prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U);
 883         prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U);
 884         prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U);
 885         prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U);
 886         prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U);
 887         prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
 888
 889         while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
 890                 ;
 891         prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
 892
 893         while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
 894                 ;
 895         for (int tp = 0; tp < 2000; tp++)
 896                 regval = Xil_In32(0xFD070018);
 897
 898         prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U);
 899         prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
 900         prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
 901         prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U);
 902         prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
 903         for (int tp = 0; tp < 2000; tp++)
 904                 regval = Xil_In32(0xFD070018);
 905
 906         prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
 907         Xil_Out32(0xFD080004, 0x0014FE01);
 908
 909         regval = Xil_In32(0xFD080030);
 910         while (regval != 0x8000007E)
 911                 regval = Xil_In32(0xFD080030);
 912
 913         Xil_Out32(0xFD080200U, 0x000091C7U);
 914         regval = Xil_In32(0xFD080030);
 915         while (regval != 0x80008FFF)
 916                 regval = Xil_In32(0xFD080030);
 917
 918         Xil_Out32(0xFD080200U, 0x800091C7U);
 919         regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
 920         if (regval != 0)
 921                 return (0);
 922
 923         Xil_Out32(0xFD080200U, 0x800091C7U);
 924         int cur_R006_tREFPRD;
 925
 926         cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
 927         prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
 928
 929         prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
 930         prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
 931         prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
 932         prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
 933         prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
 934         prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
 935
 936         Xil_Out32(0xFD080004, 0x00060001);
 937         regval = Xil_In32(0xFD080030);
 938         while ((regval & 0x80004001) != 0x80004001)
 939                 regval = Xil_In32(0xFD080030);
 940
 941         prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
 942         prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
 943         prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
 944         prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
 945         prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
 946         prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
 947
 948         Xil_Out32(0xFD080200U, 0x800091C7U);
 949         prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
 950
 951         Xil_Out32(0xFD080004, 0x0000C001);
 952         regval = Xil_In32(0xFD080030);
 953         while ((regval & 0x80000C01) != 0x80000C01)
 954                 regval = Xil_In32(0xFD080030);
 955
 956         prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U);
 957         prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
 958         prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U);
 959         prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U);
 960         Xil_Out32(0xFD070180U, 0x02160010U);
 961         Xil_Out32(0xFD070060U, 0x00000000U);
 962         prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
 963         for (int tp = 0; tp < 4000; tp++)
 964                 regval = Xil_In32(0xFD070018);
 965
 966         prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U);
 967         prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U);
 968         prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U);
 969         prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U);
 970         prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U);
 971         prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U);
 972         prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U);
 973         prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U);
 974         prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U);
 975         prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U);
 976         prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U);
 977         prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U);
 978         prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U);
 979         prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U);
 980         prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U);
 981         prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U);
 982         prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
 983         prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
 984         prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
 985         prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
 986         prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
 987         prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
 988         prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U);
 989         prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU);
 990         prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U);
 991
 992         return 1;
 993 }
 994
 995 static int serdes_enb_coarse_saturation(void)
 996 {
 997         Xil_Out32(0xFD402094, 0x00000010);
 998         Xil_Out32(0xFD406094, 0x00000010);
 999         Xil_Out32(0xFD40A094, 0x00000010);
1000         Xil_Out32(0xFD40E094, 0x00000010);
1001         return 1;
1002 }
1003
1004 static int serdes_fixcal_code(void)
1005 {
1006         int maskstatus = 1;
1007         unsigned int rdata = 0;
1008         unsigned int match_pmos_code[23];
1009         unsigned int match_nmos_code[23];
1010         unsigned int match_ical_code[7];
1011         unsigned int match_rcal_code[7];
1012         unsigned int p_code = 0;
1013         unsigned int n_code = 0;
1014         unsigned int i_code = 0;
1015         unsigned int r_code = 0;
1016         unsigned int repeat_count = 0;
1017         unsigned int L3_TM_CALIB_DIG20 = 0;
1018         unsigned int L3_TM_CALIB_DIG19 = 0;
1019         unsigned int L3_TM_CALIB_DIG18 = 0;
1020         unsigned int L3_TM_CALIB_DIG16 = 0;
1021         unsigned int L3_TM_CALIB_DIG15 = 0;
1022         unsigned int L3_TM_CALIB_DIG14 = 0;
1023         int i = 0, count = 0;
1024
1025         rdata = Xil_In32(0xFD40289C);
1026         rdata = rdata & ~0x03;
1027         rdata = rdata | 0x1;
1028         Xil_Out32(0xFD40289C, rdata);
1029
1030         do {
1031                 if (count == 1100000)
1032                         break;
1033                 rdata = Xil_In32(0xFD402B1C);
1034                 count++;
1035         } while ((rdata & 0x0000000E) != 0x0000000E);
1036
1037         for (i = 0; i < 23; i++) {
1038                 match_pmos_code[i] = 0;
1039                 match_nmos_code[i] = 0;
1040         }
1041         for (i = 0; i < 7; i++) {
1042                 match_ical_code[i] = 0;
1043                 match_rcal_code[i] = 0;
1044         }
1045
1046         do {
1047                 Xil_Out32(0xFD410010, 0x00000000);
1048                 Xil_Out32(0xFD410014, 0x00000000);
1049
1050                 Xil_Out32(0xFD410010, 0x00000001);
1051                 Xil_Out32(0xFD410014, 0x00000000);
1052
1053                 maskstatus = mask_poll(0xFD40EF14, 0x2);
1054                 if (maskstatus == 0) {
1055                         xil_printf("#SERDES initialization timed out\n\r");
1056                         return maskstatus;
1057                 }
1058
1059                 p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
1060                 n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
1061                 ;
1062                 i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
1063                 r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
1064                 ;
1065
1066                 if (p_code >= 0x26 && p_code <= 0x3C)
1067                         match_pmos_code[p_code - 0x26] += 1;
1068
1069                 if (n_code >= 0x26 && n_code <= 0x3C)
1070                         match_nmos_code[n_code - 0x26] += 1;
1071
1072                 if (i_code >= 0xC && i_code <= 0x12)
1073                         match_ical_code[i_code - 0xC] += 1;
1074
1075                 if (r_code >= 0x6 && r_code <= 0xC)
1076                         match_rcal_code[r_code - 0x6] += 1;
1077
1078         } while (repeat_count++ < 10);
1079
1080         for (i = 0; i < 23; i++) {
1081                 if (match_pmos_code[i] >= match_pmos_code[0]) {
1082                         match_pmos_code[0] = match_pmos_code[i];
1083                         p_code = 0x26 + i;
1084                 }
1085                 if (match_nmos_code[i] >= match_nmos_code[0]) {
1086                         match_nmos_code[0] = match_nmos_code[i];
1087                         n_code = 0x26 + i;
1088                 }
1089         }
1090
1091         for (i = 0; i < 7; i++) {
1092                 if (match_ical_code[i] >= match_ical_code[0]) {
1093                         match_ical_code[0] = match_ical_code[i];
1094                         i_code = 0xC + i;
1095                 }
1096                 if (match_rcal_code[i] >= match_rcal_code[0]) {
1097                         match_rcal_code[0] = match_rcal_code[i];
1098                         r_code = 0x6 + i;
1099                 }
1100         }
1101
1102         L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
1103         L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
1104
1105         L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
1106         L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
1107             | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
1108
1109         L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
1110         L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
1111
1112         L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
1113         L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
1114
1115         L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
1116         L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
1117             | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
1118
1119         L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
1120         L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
1121
1122         Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
1123         Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
1124         Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
1125         Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
1126         Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
1127         Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
1128         return maskstatus;
1129 }
1130
1131 static int init_serdes(void)
1132 {
1133         int status = 1;
1134
1135         status &= psu_resetin_init_data();
1136
1137         status &= serdes_fixcal_code();
1138         status &= serdes_enb_coarse_saturation();
1139
1140         status &= psu_serdes_init_data();
1141         status &= psu_resetout_init_data();
1142
1143         return status;
1144 }
1145
1146 static void init_peripheral(void)
1147 {
1148         psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
1149 }
1150
1151 int psu_init(void)
1152 {
1153         int status = 1;
1154
1155         status &= psu_mio_init_data();
1156         status &= psu_peripherals_pre_init_data();
1157         status &= psu_pll_init_data();
1158         status &= psu_clock_init_data();
1159         status &= psu_ddr_init_data();
1160         status &= psu_ddr_phybringup_data();
1161         status &= psu_peripherals_init_data();
1162         status &= init_serdes();
1163         init_peripheral();
1164
1165         status &= psu_afi_config();
1166         psu_ddr_qos_init_data();
1167
1168         if (status == 0)
1169                 return 1;
1170         return 0;
1171 }