1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP SoC Tap Delay Programming
5 * Copyright (C) 2018 Xilinx, Inc.
9 #include <asm/arch/sys_proto.h>
10 #include <linux/delay.h>
12 #define SD_DLL_CTRL 0xFF180358
13 #define SD_ITAP_DLY 0xFF180314
14 #define SD_OTAP_DLY 0xFF180318
15 #define SD0_DLL_RST_MASK 0x00000004
16 #define SD0_DLL_RST 0x00000004
17 #define SD1_DLL_RST_MASK 0x00040000
18 #define SD1_DLL_RST 0x00040000
19 #define SD0_ITAPCHGWIN_MASK 0x00000200
20 #define SD0_ITAPCHGWIN 0x00000200
21 #define SD1_ITAPCHGWIN_MASK 0x02000000
22 #define SD1_ITAPCHGWIN 0x02000000
23 #define SD0_ITAPDLYENA_MASK 0x00000100
24 #define SD0_ITAPDLYENA 0x00000100
25 #define SD1_ITAPDLYENA_MASK 0x01000000
26 #define SD1_ITAPDLYENA 0x01000000
27 #define SD0_ITAPDLYSEL_MASK 0x000000FF
28 #define SD0_ITAPDLYSEL_HSD 0x00000015
29 #define SD0_ITAPDLYSEL_SD_DDR50 0x0000003D
30 #define SD0_ITAPDLYSEL_MMC_DDR50 0x00000012
32 #define SD1_ITAPDLYSEL_MASK 0x00FF0000
33 #define SD1_ITAPDLYSEL_HSD 0x00150000
34 #define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000
35 #define SD1_ITAPDLYSEL_MMC_DDR50 0x00120000
37 #define SD0_OTAPDLYSEL_MASK 0x0000003F
38 #define SD0_OTAPDLYSEL_MMC_HSD 0x00000006
39 #define SD0_OTAPDLYSEL_SD_HSD 0x00000005
40 #define SD0_OTAPDLYSEL_SDR50 0x00000003
41 #define SD0_OTAPDLYSEL_SDR104_B0 0x00000003
42 #define SD0_OTAPDLYSEL_SDR104_B2 0x00000002
43 #define SD0_OTAPDLYSEL_SD_DDR50 0x00000004
44 #define SD0_OTAPDLYSEL_MMC_DDR50 0x00000006
46 #define SD1_OTAPDLYSEL_MASK 0x003F0000
47 #define SD1_OTAPDLYSEL_MMC_HSD 0x00060000
48 #define SD1_OTAPDLYSEL_SD_HSD 0x00050000
49 #define SD1_OTAPDLYSEL_SDR50 0x00030000
50 #define SD1_OTAPDLYSEL_SDR104_B0 0x00030000
51 #define SD1_OTAPDLYSEL_SDR104_B2 0x00020000
52 #define SD1_OTAPDLYSEL_SD_DDR50 0x00040000
53 #define SD1_OTAPDLYSEL_MMC_DDR50 0x00060000
57 #define MMC_TIMING_UHS_SDR25 1
58 #define MMC_TIMING_UHS_SDR50 2
59 #define MMC_TIMING_UHS_SDR104 3
60 #define MMC_TIMING_UHS_DDR50 4
61 #define MMC_TIMING_MMC_HS200 5
62 #define MMC_TIMING_SD_HS 6
63 #define MMC_TIMING_MMC_DDR52 7
64 #define MMC_TIMING_MMC_HS 8
66 void zynqmp_dll_reset(u8 deviceid)
70 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
73 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
78 /* Release DLL Reset */
80 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
82 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
85 static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank)
89 if (bank == MMC_BANK2)
90 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
91 SD0_OTAPDLYSEL_SDR104_B2);
93 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
94 SD0_OTAPDLYSEL_SDR104_B0);
97 if (bank == MMC_BANK2)
98 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
99 SD1_OTAPDLYSEL_SDR104_B2);
101 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
102 SD1_OTAPDLYSEL_SDR104_B0);
106 static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank)
110 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
112 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
114 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
116 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
118 if (timing == MMC_TIMING_MMC_HS)
119 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
120 SD0_OTAPDLYSEL_MMC_HSD);
122 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
123 SD0_OTAPDLYSEL_SD_HSD);
126 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
128 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
130 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
132 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
134 if (timing == MMC_TIMING_MMC_HS)
135 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
136 SD1_OTAPDLYSEL_MMC_HSD);
138 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
139 SD1_OTAPDLYSEL_SD_HSD);
143 static void arasan_zynqmp_tap_ddr50(u8 deviceid, u8 timing, u8 bank)
147 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
149 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
151 if (timing == MMC_TIMING_UHS_DDR50)
152 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
153 SD0_ITAPDLYSEL_SD_DDR50);
155 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
156 SD0_ITAPDLYSEL_MMC_DDR50);
157 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
159 if (timing == MMC_TIMING_UHS_DDR50)
160 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
161 SD0_OTAPDLYSEL_SD_DDR50);
163 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
164 SD0_OTAPDLYSEL_MMC_DDR50);
167 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
169 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
171 if (timing == MMC_TIMING_UHS_DDR50)
172 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
173 SD1_ITAPDLYSEL_SD_DDR50);
175 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
176 SD1_ITAPDLYSEL_MMC_DDR50);
177 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
179 if (timing == MMC_TIMING_UHS_DDR50)
180 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
181 SD1_OTAPDLYSEL_SD_DDR50);
183 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
184 SD1_OTAPDLYSEL_MMC_DDR50);
188 static void arasan_zynqmp_tap_sdr50(u8 deviceid, u8 timing, u8 bank)
192 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
193 SD0_OTAPDLYSEL_SDR50);
196 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
197 SD1_OTAPDLYSEL_SDR50);
201 void arasan_zynqmp_set_tapdelay(u8 deviceid, u8 timing, u8 bank)
204 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
207 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
211 case MMC_TIMING_UHS_SDR25:
212 arasan_zynqmp_tap_hs(deviceid, timing, bank);
214 case MMC_TIMING_UHS_SDR50:
215 arasan_zynqmp_tap_sdr50(deviceid, timing, bank);
217 case MMC_TIMING_UHS_SDR104:
218 case MMC_TIMING_MMC_HS200:
219 arasan_zynqmp_tap_sdr104(deviceid, timing, bank);
221 case MMC_TIMING_UHS_DDR50:
222 arasan_zynqmp_tap_ddr50(deviceid, timing, bank);
227 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
229 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);