2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
3 * (C) Copyright 2013 - 2018 Xilinx, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/ps7_init_gpl.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
22 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
23 static xilinx_desc fpga;
25 /* It can be done differently */
26 static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
27 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
28 static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
29 static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
30 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
31 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
32 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
33 static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
34 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
35 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
38 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
39 static struct udevice *watchdog_dev;
42 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)
43 int board_early_init_f(void)
45 # if defined(CONFIG_WDT)
46 /* bss is not cleared at time when watchdog_reset() is called */
56 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
57 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
60 idcode = zynq_slcr_get_idcode();
63 case XILINX_ZYNQ_7007S:
66 case XILINX_ZYNQ_7010:
69 case XILINX_ZYNQ_7012S:
72 case XILINX_ZYNQ_7014S:
75 case XILINX_ZYNQ_7015:
78 case XILINX_ZYNQ_7020:
81 case XILINX_ZYNQ_7030:
84 case XILINX_ZYNQ_7035:
87 case XILINX_ZYNQ_7045:
90 case XILINX_ZYNQ_7100:
96 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
97 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
98 puts("Watchdog: Not found!\n");
100 wdt_start(watchdog_dev, 0, 0);
101 puts("Watchdog: Started\n");
105 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
106 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
108 fpga_add(fpga_xilinx, &fpga);
114 int board_late_init(void)
116 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
118 env_set("modeboot", "qspiboot");
121 env_set("modeboot", "nandboot");
124 env_set("modeboot", "norboot");
127 env_set("modeboot", "sdboot");
130 env_set("modeboot", "jtagboot");
133 env_set("modeboot", "");
140 #ifdef CONFIG_DISPLAY_BOARDINFO
143 u32 version = zynq_get_silicon_version();
146 if (version > (PCW_SILICON_VERSION_3 << 1))
149 puts("Board: Xilinx Zynq\n");
150 printf("Silicon: v%d.%d\n", version >> 1, version & 1);
156 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
158 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
159 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
160 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
161 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
163 printf("I2C EEPROM MAC address read failed\n");
169 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
170 int dram_init_banksize(void)
172 return fdtdec_setup_memory_banksize();
177 if (fdtdec_setup_memory_size() != 0)
187 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
188 CONFIG_SYS_SDRAM_SIZE);
196 #if defined(CONFIG_WATCHDOG)
197 /* Called by macro WATCHDOG_RESET */
198 void watchdog_reset(void)
200 # if !defined(CONFIG_SPL_BUILD)
201 static ulong next_reset;
207 now = timer_get_us();
209 /* Do not reset the watchdog too often */
210 if (now > next_reset) {
211 wdt_reset(watchdog_dev);
212 next_reset = now + 1000;