1 /******************************************************************************
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25 * Xilinx hardware products are not intended for use in life support
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30 * (c) Copyright 2002-2004 Xilinx Inc.
31 * All rights reserved.
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 ******************************************************************************/
39 /*****************************************************************************/
44 * This file contains general interrupt-related functions of the XEmac driver.
47 * MODIFICATION HISTORY:
49 * Ver Who Date Changes
50 * ----- ---- -------- -----------------------------------------------
51 * 1.00a rpm 07/31/01 First release
52 * 1.00b rpm 02/20/02 Repartitioned files and functions
53 * 1.00c rpm 12/05/02 New version includes support for simple DMA
54 * 1.00c rpm 03/31/03 Added comment to indicate that no Receive Length FIFO
55 * overrun interrupts occur in v1.00l and later of the EMAC
56 * device. This avoids the need to reset the device on
60 ******************************************************************************/
62 /***************************** Include Files *********************************/
64 #include "xbasic_types.h"
67 #include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */
69 /************************** Constant Definitions *****************************/
71 /**************************** Type Definitions *******************************/
73 /***************** Macros (Inline Functions) Definitions *********************/
75 /************************** Variable Definitions *****************************/
77 /************************** Function Prototypes ******************************/
79 /*****************************************************************************/
82 * Set the callback function for handling asynchronous errors. The upper layer
83 * software should call this function during initialization.
85 * The error callback is invoked by the driver within interrupt context, so it
86 * needs to do its job quickly. If there are potentially slow operations within
87 * the callback, these should be done at task-level.
89 * The Xilinx errors that must be handled by the callback are:
90 * - XST_DMA_ERROR indicates an unrecoverable DMA error occurred. This is
91 * typically a bus error or bus timeout. The handler must reset and
92 * re-configure the device.
93 * - XST_FIFO_ERROR indicates an unrecoverable FIFO error occurred. This is a
94 * deadlock condition in the packet FIFO. The handler must reset and
95 * re-configure the device.
96 * - XST_RESET_ERROR indicates an unrecoverable MAC error occurred, usually an
97 * overrun or underrun. The handler must reset and re-configure the device.
98 * - XST_DMA_SG_NO_LIST indicates an attempt was made to access a scatter-gather
99 * DMA list that has not yet been created.
100 * - XST_DMA_SG_LIST_EMPTY indicates the driver tried to get a descriptor from
101 * the receive descriptor list, but the list was empty.
103 * @param InstancePtr is a pointer to the XEmac instance to be worked on.
104 * @param CallBackRef is a reference pointer to be passed back to the adapter in
105 * the callback. This helps the adapter correlate the callback to a
107 * @param FuncPtr is the pointer to the callback function.
117 ******************************************************************************/
119 XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef,
120 XEmac_ErrorHandler FuncPtr)
122 XASSERT_VOID(InstancePtr != NULL);
123 XASSERT_VOID(FuncPtr != NULL);
124 XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
126 InstancePtr->ErrorHandler = FuncPtr;
127 InstancePtr->ErrorRef = CallBackRef;
130 /****************************************************************************/
133 * Check the interrupt status bits of the Ethernet MAC for errors. Errors
134 * currently handled are:
135 * - Receive length FIFO overrun. Indicates data was lost due to the receive
136 * length FIFO becoming full during the reception of a packet. Only a device
137 * reset clears this condition.
138 * - Receive length FIFO underrun. An attempt to read an empty FIFO. Only a
139 * device reset clears this condition.
140 * - Transmit status FIFO overrun. Indicates data was lost due to the transmit
141 * status FIFO becoming full following the transmission of a packet. Only a
142 * device reset clears this condition.
143 * - Transmit status FIFO underrun. An attempt to read an empty FIFO. Only a
144 * device reset clears this condition.
145 * - Transmit length FIFO overrun. Indicates data was lost due to the transmit
146 * length FIFO becoming full following the transmission of a packet. Only a
147 * device reset clears this condition.
148 * - Transmit length FIFO underrun. An attempt to read an empty FIFO. Only a
149 * device reset clears this condition.
150 * - Receive data FIFO overrun. Indicates data was lost due to the receive data
151 * FIFO becoming full during the reception of a packet.
152 * - Receive data errors:
153 * - Receive missed frame error. Valid data was lost by the MAC.
154 * - Receive collision error. Data was lost by the MAC due to a collision.
155 * - Receive FCS error. Data was dicarded by the MAC due to FCS error.
156 * - Receive length field error. Data was dicarded by the MAC due to an invalid
157 * length field in the packet.
158 * - Receive short error. Data was dicarded by the MAC because a packet was
159 * shorter than allowed.
160 * - Receive long error. Data was dicarded by the MAC because a packet was
161 * longer than allowed.
162 * - Receive alignment error. Data was truncated by the MAC because its length
163 * was not byte-aligned.
165 * @param InstancePtr is a pointer to the XEmac instance to be worked on.
166 * @param IntrStatus is the contents of the interrupt status register to be checked
174 * This function is intended for internal use only.
176 ******************************************************************************/
178 XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus)
180 u32 ResetError = FALSE;
183 * First check for receive fifo overrun/underrun errors. Most require a
184 * reset by the user to clear, but the data FIFO overrun error does not.
186 if (IntrStatus & XEM_EIR_RECV_DFIFO_OVER_MASK) {
187 InstancePtr->Stats.RecvOverrunErrors++;
188 InstancePtr->Stats.FifoErrors++;
191 if (IntrStatus & XEM_EIR_RECV_LFIFO_OVER_MASK) {
193 * Receive Length FIFO overrun interrupts no longer occur in v1.00l
194 * and later of the EMAC device. Frames are just dropped by the EMAC
195 * if the length FIFO is full. The user would notice the Receive Missed
196 * Frame count incrementing without any other errors being reported.
197 * This code is left here for backward compatibility with v1.00k and
198 * older EMAC devices.
200 InstancePtr->Stats.RecvOverrunErrors++;
201 InstancePtr->Stats.FifoErrors++;
202 ResetError = TRUE; /* requires a reset */
205 if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) {
206 InstancePtr->Stats.RecvUnderrunErrors++;
207 InstancePtr->Stats.FifoErrors++;
208 ResetError = TRUE; /* requires a reset */
212 * Now check for general receive errors. Get the latest count where
213 * available, otherwise just bump the statistic so we know the interrupt
216 if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) {
217 if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) {
219 * Caused by length FIFO or data FIFO overruns on receive side
221 InstancePtr->Stats.RecvMissedFrameErrors =
222 XIo_In32(InstancePtr->BaseAddress +
226 if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) {
227 InstancePtr->Stats.RecvCollisionErrors =
228 XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET);
231 if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) {
232 InstancePtr->Stats.RecvFcsErrors =
233 XIo_In32(InstancePtr->BaseAddress +
237 if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) {
238 InstancePtr->Stats.RecvLengthFieldErrors++;
241 if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) {
242 InstancePtr->Stats.RecvShortErrors++;
245 if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) {
246 InstancePtr->Stats.RecvLongErrors++;
249 if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) {
250 InstancePtr->Stats.RecvAlignmentErrors =
251 XIo_In32(InstancePtr->BaseAddress +
256 * Bump recv interrupts stats only if not scatter-gather DMA (this
257 * stat gets bumped elsewhere in that case)
259 if (!XEmac_mIsSgDma(InstancePtr)) {
260 InstancePtr->Stats.RecvInterrupts++; /* TODO: double bump? */
266 * Check for transmit errors. These apply to both DMA and non-DMA modes
267 * of operation. The entire device should be reset after overruns or
270 if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
271 XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
272 InstancePtr->Stats.XmitOverrunErrors++;
273 InstancePtr->Stats.FifoErrors++;
277 if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
278 XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
279 InstancePtr->Stats.XmitUnderrunErrors++;
280 InstancePtr->Stats.FifoErrors++;
286 * If a reset error occurred, disable the EMAC interrupts since the
287 * reset-causing interrupt(s) is latched in the EMAC - meaning it will
288 * keep occurring until the device is reset. In order to give the higher
289 * layer software time to reset the device, we have to disable the
290 * overrun/underrun interrupts until that happens. We trust that the
291 * higher layer resets the device. We are able to get away with disabling
292 * all EMAC interrupts since the only interrupts it generates are for
293 * error conditions, and we don't care about any more errors right now.
295 XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress, 0);
298 * Invoke the error handler callback, which should result in a reset
299 * of the device by the upper layer software.
301 InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
306 /*****************************************************************************/
309 * Check the receive packet FIFO for errors. FIFO error interrupts are:
310 * - Deadlock. See the XPacketFifo component for a description of deadlock on a
313 * @param InstancePtr is a pointer to the XEmac instance to be worked on.
317 * Although the function returns void, it can return an asynchronous error to the
318 * application through the error handler. It can return XST_FIFO_ERROR if a FIFO
323 * This function is intended for internal use only.
325 ******************************************************************************/
327 XEmac_CheckFifoRecvError(XEmac * InstancePtr)
330 * Although the deadlock is currently the only interrupt from a packet
331 * FIFO, make sure it is deadlocked before taking action. There is no
332 * need to clear this interrupt since it requires a reset of the device.
334 if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->RecvFifo)) {
337 InstancePtr->Stats.FifoErrors++;
340 * Invoke the error callback function, which should result in a reset
341 * of the device by the upper layer software. We first need to disable
342 * the FIFO interrupt, since otherwise the upper layer thread that
343 * handles the reset may never run because this interrupt condition
344 * doesn't go away until a reset occurs (there is no way to ack it).
346 IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress);
347 XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
348 IntrEnable & ~XEM_IPIF_RECV_FIFO_MASK);
350 InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
355 /*****************************************************************************/
358 * Check the send packet FIFO for errors. FIFO error interrupts are:
359 * - Deadlock. See the XPacketFifo component for a description of deadlock on a
362 * @param InstancePtr is a pointer to the XEmac instance to be worked on.
366 * Although the function returns void, it can return an asynchronous error to the
367 * application through the error handler. It can return XST_FIFO_ERROR if a FIFO
372 * This function is intended for internal use only.
374 ******************************************************************************/
376 XEmac_CheckFifoSendError(XEmac * InstancePtr)
379 * Although the deadlock is currently the only interrupt from a packet
380 * FIFO, make sure it is deadlocked before taking action. There is no
381 * need to clear this interrupt since it requires a reset of the device.
383 if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->SendFifo)) {
386 InstancePtr->Stats.FifoErrors++;
389 * Invoke the error callback function, which should result in a reset
390 * of the device by the upper layer software. We first need to disable
391 * the FIFO interrupt, since otherwise the upper layer thread that
392 * handles the reset may never run because this interrupt condition
393 * doesn't go away until a reset occurs (there is no way to ack it).
395 IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress);
396 XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
397 IntrEnable & ~XEM_IPIF_SEND_FIFO_MASK);
399 InstancePtr->ErrorHandler(InstancePtr->ErrorRef,