1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
11 #include <asm/arch/hardware.h>
13 DECLARE_GLOBAL_DATA_PTR;
17 printf("EL Level:\tEL%d\n", current_el());
22 int board_early_init_r(void)
24 if (current_el() == 3) {
27 writel(IOU_SWITCH_CTRL_CLKACT_BIT |
28 (0x20 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
29 &crlapb_base->iou_switch_ctrl);
31 /* Global timer init - Program time stamp reference clk */
32 val = readl(&crlapb_base->timestamp_ref_ctrl);
33 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
34 writel(val, &crlapb_base->timestamp_ref_ctrl);
36 debug("ref ctrl 0x%x\n",
37 readl(&crlapb_base->timestamp_ref_ctrl));
39 /* Clear reset of timestamp reg */
40 writel(0, &crlapb_base->rst_timestamp);
43 * Program freq register in System counter and
44 * enable system counter.
46 writel(COUNTER_FREQUENCY,
47 &iou_scntr_secure->base_frequency_id_register);
49 debug("counter val 0x%x\n",
50 readl(&iou_scntr_secure->base_frequency_id_register));
52 writel(IOU_SCNTRS_CONTROL_EN,
53 &iou_scntr_secure->counter_control_register);
55 debug("scntrs control 0x%x\n",
56 readl(&iou_scntr_secure->counter_control_register));
57 debug("timer 0x%llx\n", get_ticks());
58 debug("timer 0x%llx\n", get_ticks());
64 int dram_init_banksize(void)
66 fdtdec_setup_memory_banksize();
73 if (fdtdec_setup_mem_size_base() != 0)
79 void reset_cpu(ulong addr)