board/xilinx/versal/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2018 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <fdtdec.h>
   9 #include <malloc.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/hardware.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 int board_init(void)
  16 {
  17         printf("EL Level:\tEL%d\n", current_el());
  18
  19         return 0;
  20 }
  21
  22 int board_early_init_r(void)
  23 {
  24         if (current_el() == 3) {
  25                 u32 val;
  26
  27                 writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  28                        (0x20 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  29                        &crlapb_base->iou_switch_ctrl);
  30
  31                 /* Global timer init - Program time stamp reference clk */
  32                 val = readl(&crlapb_base->timestamp_ref_ctrl);
  33                 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  34                 writel(val, &crlapb_base->timestamp_ref_ctrl);
  35
  36                 debug("ref ctrl 0x%x\n",
  37                       readl(&crlapb_base->timestamp_ref_ctrl));
  38
  39                 /* Clear reset of timestamp reg */
  40                 writel(0, &crlapb_base->rst_timestamp);
  41
  42                 /*
  43                  * Program freq register in System counter and
  44                  * enable system counter.
  45                  */
  46                 writel(COUNTER_FREQUENCY,
  47                        &iou_scntr_secure->base_frequency_id_register);
  48
  49                 debug("counter val 0x%x\n",
  50                       readl(&iou_scntr_secure->base_frequency_id_register));
  51
  52                 writel(IOU_SCNTRS_CONTROL_EN,
  53                        &iou_scntr_secure->counter_control_register);
  54
  55                 debug("scntrs control 0x%x\n",
  56                       readl(&iou_scntr_secure->counter_control_register));
  57                 debug("timer 0x%llx\n", get_ticks());
  58                 debug("timer 0x%llx\n", get_ticks());
  59         }
  60
  61         return 0;
  62 }
  63
  64 int dram_init_banksize(void)
  65 {
  66         fdtdec_setup_memory_banksize();
  67
  68         return 0;
  69 }
  70
  71 int dram_init(void)
  72 {
  73         if (fdtdec_setup_mem_size_base() != 0)
  74                 return -EINVAL;
  75
  76         return 0;
  77 }
  78
  79 void reset_cpu(ulong addr)
  80 {
  81 }