board/xilinx/versal/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2018 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <fdtdec.h>
   9 #include <malloc.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/hardware.h>
  12 #include <dm/device.h>
  13 #include <dm/uclass.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 int board_init(void)
  18 {
  19         printf("EL Level:\tEL%d\n", current_el());
  20
  21         return 0;
  22 }
  23
  24 int board_early_init_r(void)
  25 {
  26         u32 val;
  27
  28         if (current_el() != 3)
  29                 return 0;
  30
  31         debug("iou_switch ctrl div0 %x\n",
  32               readl(&crlapb_base->iou_switch_ctrl));
  33
  34         writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  35                (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  36                &crlapb_base->iou_switch_ctrl);
  37
  38         /* Global timer init - Program time stamp reference clk */
  39         val = readl(&crlapb_base->timestamp_ref_ctrl);
  40         val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  41         writel(val, &crlapb_base->timestamp_ref_ctrl);
  42
  43         debug("ref ctrl 0x%x\n",
  44               readl(&crlapb_base->timestamp_ref_ctrl));
  45
  46         /* Clear reset of timestamp reg */
  47         writel(0, &crlapb_base->rst_timestamp);
  48
  49         /*
  50          * Program freq register in System counter and
  51          * enable system counter.
  52          */
  53         writel(COUNTER_FREQUENCY,
  54                &iou_scntr_secure->base_frequency_id_register);
  55
  56         debug("counter val 0x%x\n",
  57               readl(&iou_scntr_secure->base_frequency_id_register));
  58
  59         writel(IOU_SCNTRS_CONTROL_EN,
  60                &iou_scntr_secure->counter_control_register);
  61
  62         debug("scntrs control 0x%x\n",
  63               readl(&iou_scntr_secure->counter_control_register));
  64         debug("timer 0x%llx\n", get_ticks());
  65         debug("timer 0x%llx\n", get_ticks());
  66
  67         return 0;
  68 }
  69
  70 int board_late_init(void)
  71 {
  72         u32 reg = 0;
  73         u8 bootmode;
  74         struct udevice *dev;
  75         int bootseq = -1;
  76         int bootseq_len = 0;
  77         int env_targets_len = 0;
  78         const char *mode;
  79         char *new_targets;
  80         char *env_targets;
  81
  82         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  83                 debug("Saved variables - Skipping\n");
  84                 return 0;
  85         }
  86
  87         reg = readl(&crp_base->boot_mode_usr);
  88
  89         if (reg >> BOOT_MODE_ALT_SHIFT)
  90                 reg >>= BOOT_MODE_ALT_SHIFT;
  91
  92         bootmode = reg & BOOT_MODES_MASK;
  93
  94         puts("Bootmode: ");
  95         switch (bootmode) {
  96         case JTAG_MODE:
  97                 puts("JTAG_MODE\n");
  98                 mode = "pxe dhcp";
  99                 break;
 100         case QSPI_MODE_24BIT:
 101                 puts("QSPI_MODE_24\n");
 102                 mode = "xspi0";
 103                 break;
 104         case QSPI_MODE_32BIT:
 105                 puts("QSPI_MODE_32\n");
 106                 mode = "xspi0";
 107                 break;
 108         case OSPI_MODE:
 109                 puts("OSPI_MODE\n");
 110                 mode = "xspi0";
 111                 break;
 112         case EMMC_MODE:
 113                 puts("EMMC_MODE\n");
 114                 mode = "mmc0";
 115                 break;
 116         case SD_MODE:
 117                 puts("SD_MODE\n");
 118                 if (uclass_get_device_by_name(UCLASS_MMC,
 119                                               "sdhci@f1040000", &dev)) {
 120                         puts("Boot from SD0 but without SD0 enabled!\n");
 121                         return -1;
 122                 }
 123                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 124
 125                 mode = "mmc";
 126                 bootseq = dev->seq;
 127                 break;
 128         case SD1_LSHFT_MODE:
 129                 puts("LVL_SHFT_");
 130                 /* fall through */
 131         case SD_MODE1:
 132                 puts("SD_MODE1\n");
 133                 if (uclass_get_device_by_name(UCLASS_MMC,
 134                                               "sdhci@f1050000", &dev)) {
 135                         puts("Boot from SD1 but without SD1 enabled!\n");
 136                         return -1;
 137                 }
 138                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 139
 140                 mode = "mmc";
 141                 bootseq = dev->seq;
 142                 break;
 143         default:
 144                 mode = "";
 145                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 146                 break;
 147         }
 148
 149         if (bootseq >= 0) {
 150                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 151                 debug("Bootseq len: %x\n", bootseq_len);
 152         }
 153
 154         /*
 155          * One terminating char + one byte for space between mode
 156          * and default boot_targets
 157          */
 158         env_targets = env_get("boot_targets");
 159         if (env_targets)
 160                 env_targets_len = strlen(env_targets);
 161
 162         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 163                              bootseq_len);
 164         if (!new_targets)
 165                 return -ENOMEM;
 166
 167         if (bootseq >= 0)
 168                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 169                         env_targets ? env_targets : "");
 170         else
 171                 sprintf(new_targets, "%s %s", mode,
 172                         env_targets ? env_targets : "");
 173
 174         env_set("boot_targets", new_targets);
 175
 176         return 0;
 177 }
 178
 179 int dram_init_banksize(void)
 180 {
 181         fdtdec_setup_memory_banksize();
 182
 183         return 0;
 184 }
 185
 186 int dram_init(void)
 187 {
 188         if (fdtdec_setup_mem_size_base() != 0)
 189                 return -EINVAL;
 190
 191         return 0;
 192 }
 193
 194 void reset_cpu(ulong addr)
 195 {
 196 }