1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
16 #include <dm/device.h>
17 #include <dm/uclass.h>
19 #include "../common/board.h"
21 DECLARE_GLOBAL_DATA_PTR;
23 #if defined(CONFIG_FPGA_VERSALPL)
24 static xilinx_desc versalpl = XILINX_VERSAL_DESC;
29 printf("EL Level:\tEL%d\n", current_el());
31 #if defined(CONFIG_FPGA_VERSALPL)
33 fpga_add(fpga_xilinx, &versalpl);
39 int board_early_init_r(void)
43 if (current_el() != 3)
46 debug("iou_switch ctrl div0 %x\n",
47 readl(&crlapb_base->iou_switch_ctrl));
49 writel(IOU_SWITCH_CTRL_CLKACT_BIT |
50 (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
51 &crlapb_base->iou_switch_ctrl);
53 /* Global timer init - Program time stamp reference clk */
54 val = readl(&crlapb_base->timestamp_ref_ctrl);
55 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
56 writel(val, &crlapb_base->timestamp_ref_ctrl);
58 debug("ref ctrl 0x%x\n",
59 readl(&crlapb_base->timestamp_ref_ctrl));
61 /* Clear reset of timestamp reg */
62 writel(0, &crlapb_base->rst_timestamp);
65 * Program freq register in System counter and
66 * enable system counter.
68 writel(COUNTER_FREQUENCY,
69 &iou_scntr_secure->base_frequency_id_register);
71 debug("counter val 0x%x\n",
72 readl(&iou_scntr_secure->base_frequency_id_register));
74 writel(IOU_SCNTRS_CONTROL_EN,
75 &iou_scntr_secure->counter_control_register);
77 debug("scntrs control 0x%x\n",
78 readl(&iou_scntr_secure->counter_control_register));
79 debug("timer 0x%llx\n", get_ticks());
80 debug("timer 0x%llx\n", get_ticks());
85 static u8 versal_get_bootmode(void)
90 reg = readl(&crp_base->boot_mode_usr);
92 if (reg >> BOOT_MODE_ALT_SHIFT)
93 reg >>= BOOT_MODE_ALT_SHIFT;
95 bootmode = reg & BOOT_MODES_MASK;
100 int board_late_init(void)
106 int env_targets_len = 0;
111 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
112 debug("Saved variables - Skipping\n");
116 bootmode = versal_get_bootmode();
126 mode = "jtag pxe dhcp";
128 case QSPI_MODE_24BIT:
129 puts("QSPI_MODE_24\n");
132 case QSPI_MODE_32BIT:
133 puts("QSPI_MODE_32\n");
142 if (uclass_get_device_by_name(UCLASS_MMC,
143 "sdhci@f1050000", &dev)) {
144 puts("Boot from EMMC but without SD1 enabled!\n");
147 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
153 if (uclass_get_device_by_name(UCLASS_MMC,
154 "sdhci@f1040000", &dev)) {
155 puts("Boot from SD0 but without SD0 enabled!\n");
158 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
168 if (uclass_get_device_by_name(UCLASS_MMC,
169 "sdhci@f1050000", &dev)) {
170 puts("Boot from SD1 but without SD1 enabled!\n");
173 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
180 printf("Invalid Boot Mode:0x%x\n", bootmode);
185 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
186 debug("Bootseq len: %x\n", bootseq_len);
190 * One terminating char + one byte for space between mode
191 * and default boot_targets
193 env_targets = env_get("boot_targets");
195 env_targets_len = strlen(env_targets);
197 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
203 sprintf(new_targets, "%s%x %s", mode, bootseq,
204 env_targets ? env_targets : "");
206 sprintf(new_targets, "%s %s", mode,
207 env_targets ? env_targets : "");
209 env_set("boot_targets", new_targets);
211 return board_late_init_xilinx();
214 int dram_init_banksize(void)
218 ret = fdtdec_setup_memory_banksize();
229 if (fdtdec_setup_mem_size_base() != 0)
235 void reset_cpu(ulong addr)