1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/sys_proto.h>
15 #include <dm/device.h>
16 #include <dm/uclass.h>
18 #include <linux/sizes.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #if defined(CONFIG_FPGA_VERSALPL)
23 static xilinx_desc versalpl = XILINX_VERSAL_DESC;
28 printf("EL Level:\tEL%d\n", current_el());
30 #if defined(CONFIG_FPGA_VERSALPL)
32 fpga_add(fpga_xilinx, &versalpl);
38 int board_early_init_r(void)
42 if (current_el() != 3)
45 debug("iou_switch ctrl div0 %x\n",
46 readl(&crlapb_base->iou_switch_ctrl));
48 writel(IOU_SWITCH_CTRL_CLKACT_BIT |
49 (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
50 &crlapb_base->iou_switch_ctrl);
52 /* Global timer init - Program time stamp reference clk */
53 val = readl(&crlapb_base->timestamp_ref_ctrl);
54 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
55 writel(val, &crlapb_base->timestamp_ref_ctrl);
57 debug("ref ctrl 0x%x\n",
58 readl(&crlapb_base->timestamp_ref_ctrl));
60 /* Clear reset of timestamp reg */
61 writel(0, &crlapb_base->rst_timestamp);
64 * Program freq register in System counter and
65 * enable system counter.
67 writel(COUNTER_FREQUENCY,
68 &iou_scntr_secure->base_frequency_id_register);
70 debug("counter val 0x%x\n",
71 readl(&iou_scntr_secure->base_frequency_id_register));
73 writel(IOU_SCNTRS_CONTROL_EN,
74 &iou_scntr_secure->counter_control_register);
76 debug("scntrs control 0x%x\n",
77 readl(&iou_scntr_secure->counter_control_register));
78 debug("timer 0x%llx\n", get_ticks());
79 debug("timer 0x%llx\n", get_ticks());
84 int board_late_init(void)
91 int env_targets_len = 0;
97 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
98 debug("Saved variables - Skipping\n");
102 reg = readl(&crp_base->boot_mode_usr);
104 if (reg >> BOOT_MODE_ALT_SHIFT)
105 reg >>= BOOT_MODE_ALT_SHIFT;
107 bootmode = reg & BOOT_MODES_MASK;
117 mode = "jtag pxe dhcp";
119 case QSPI_MODE_24BIT:
120 puts("QSPI_MODE_24\n");
123 case QSPI_MODE_32BIT:
124 puts("QSPI_MODE_32\n");
137 if (uclass_get_device_by_name(UCLASS_MMC,
138 "sdhci@f1040000", &dev)) {
139 puts("Boot from SD0 but without SD0 enabled!\n");
142 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
152 if (uclass_get_device_by_name(UCLASS_MMC,
153 "sdhci@f1050000", &dev)) {
154 puts("Boot from SD1 but without SD1 enabled!\n");
157 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
164 printf("Invalid Boot Mode:0x%x\n", bootmode);
169 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
170 debug("Bootseq len: %x\n", bootseq_len);
174 * One terminating char + one byte for space between mode
175 * and default boot_targets
177 env_targets = env_get("boot_targets");
179 env_targets_len = strlen(env_targets);
181 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
187 sprintf(new_targets, "%s%x %s", mode, bootseq,
188 env_targets ? env_targets : "");
190 sprintf(new_targets, "%s %s", mode,
191 env_targets ? env_targets : "");
193 env_set("boot_targets", new_targets);
195 initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
196 initrd_hi = round_down(initrd_hi, SZ_16M);
197 env_set_addr("initrd_high", (void *)initrd_hi);
202 int dram_init_banksize(void)
206 ret = fdtdec_setup_memory_banksize();
217 if (fdtdec_setup_mem_size_base() != 0)
223 void reset_cpu(ulong addr)