1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@amd.com>
13 #include <env_internal.h>
17 #include <asm/cache.h>
18 #include <asm/global_data.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/sys_proto.h>
22 #include <dm/device.h>
23 #include <dm/uclass.h>
25 #include "../common/board.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 #if defined(CONFIG_FPGA_VERSALPL)
30 static xilinx_desc versalpl = {
31 xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
38 printf("EL Level:\tEL%d\n", current_el());
40 #if defined(CONFIG_FPGA_VERSALPL)
42 fpga_add(fpga_xilinx, &versalpl);
45 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
51 int board_early_init_r(void)
55 if (current_el() != 3)
58 debug("iou_switch ctrl div0 %x\n",
59 readl(&crlapb_base->iou_switch_ctrl));
61 writel(IOU_SWITCH_CTRL_CLKACT_BIT |
62 (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
63 &crlapb_base->iou_switch_ctrl);
65 /* Global timer init - Program time stamp reference clk */
66 val = readl(&crlapb_base->timestamp_ref_ctrl);
67 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
68 writel(val, &crlapb_base->timestamp_ref_ctrl);
70 debug("ref ctrl 0x%x\n",
71 readl(&crlapb_base->timestamp_ref_ctrl));
73 /* Clear reset of timestamp reg */
74 writel(0, &crlapb_base->rst_timestamp);
77 * Program freq register in System counter and
78 * enable system counter.
80 writel(CONFIG_COUNTER_FREQUENCY,
81 &iou_scntr_secure->base_frequency_id_register);
83 debug("counter val 0x%x\n",
84 readl(&iou_scntr_secure->base_frequency_id_register));
86 writel(IOU_SCNTRS_CONTROL_EN,
87 &iou_scntr_secure->counter_control_register);
89 debug("scntrs control 0x%x\n",
90 readl(&iou_scntr_secure->counter_control_register));
91 debug("timer 0x%llx\n", get_ticks());
92 debug("timer 0x%llx\n", get_ticks());
97 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
102 if (current_el() > 1) {
105 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
108 printf("FAIL: current EL is not above EL1\n");
114 static u8 versal_get_bootmode(void)
119 reg = readl(&crp_base->boot_mode_usr);
121 if (reg >> BOOT_MODE_ALT_SHIFT)
122 reg >>= BOOT_MODE_ALT_SHIFT;
124 bootmode = reg & BOOT_MODES_MASK;
129 int board_late_init(void)
135 int env_targets_len = 0;
140 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
141 debug("Saved variables - Skipping\n");
145 if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
148 bootmode = versal_get_bootmode();
154 mode = "usb_dfu0 usb_dfu1";
158 mode = "jtag pxe dhcp";
160 case QSPI_MODE_24BIT:
161 puts("QSPI_MODE_24\n");
164 case QSPI_MODE_32BIT:
165 puts("QSPI_MODE_32\n");
174 if (uclass_get_device_by_name(UCLASS_MMC,
175 "mmc@f1050000", &dev) &&
176 uclass_get_device_by_name(UCLASS_MMC,
177 "sdhci@f1050000", &dev)) {
178 puts("Boot from EMMC but without SD1 enabled!\n");
181 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
183 bootseq = dev_seq(dev);
187 if (uclass_get_device_by_name(UCLASS_MMC,
188 "mmc@f1040000", &dev) &&
189 uclass_get_device_by_name(UCLASS_MMC,
190 "sdhci@f1040000", &dev)) {
191 puts("Boot from SD0 but without SD0 enabled!\n");
194 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
197 bootseq = dev_seq(dev);
204 if (uclass_get_device_by_name(UCLASS_MMC,
205 "mmc@f1050000", &dev) &&
206 uclass_get_device_by_name(UCLASS_MMC,
207 "sdhci@f1050000", &dev)) {
208 puts("Boot from SD1 but without SD1 enabled!\n");
211 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
214 bootseq = dev_seq(dev);
218 printf("Invalid Boot Mode:0x%x\n", bootmode);
223 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
224 debug("Bootseq len: %x\n", bootseq_len);
228 * One terminating char + one byte for space between mode
229 * and default boot_targets
231 env_targets = env_get("boot_targets");
233 env_targets_len = strlen(env_targets);
235 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
241 sprintf(new_targets, "%s%x %s", mode, bootseq,
242 env_targets ? env_targets : "");
244 sprintf(new_targets, "%s %s", mode,
245 env_targets ? env_targets : "");
247 env_set("boot_targets", new_targets);
249 return board_late_init_xilinx();
252 int dram_init_banksize(void)
256 ret = fdtdec_setup_memory_banksize();
267 if (fdtdec_setup_mem_size_base_lowest() != 0)
277 enum env_location env_get_location(enum env_operation op, int prio)
279 u32 bootmode = versal_get_bootmode();
289 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
291 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
295 case QSPI_MODE_24BIT:
296 case QSPI_MODE_32BIT:
297 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
298 return ENVL_SPI_FLASH;