board/xilinx/versal/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2018 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <env.h>
  10 #include <fdtdec.h>
  11 #include <init.h>
  12 #include <malloc.h>
  13 #include <time.h>
  14 #include <asm/cache.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <dm/device.h>
  19 #include <dm/uclass.h>
  20 #include <versalpl.h>
  21 #include "../common/board.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #if defined(CONFIG_FPGA_VERSALPL)
  26 static xilinx_desc versalpl = XILINX_VERSAL_DESC;
  27 #endif
  28
  29 int board_init(void)
  30 {
  31         printf("EL Level:\tEL%d\n", current_el());
  32
  33 #if defined(CONFIG_FPGA_VERSALPL)
  34         fpga_init();
  35         fpga_add(fpga_xilinx, &versalpl);
  36 #endif
  37
  38         return 0;
  39 }
  40
  41 int board_early_init_r(void)
  42 {
  43         u32 val;
  44
  45         if (current_el() != 3)
  46                 return 0;
  47
  48         debug("iou_switch ctrl div0 %x\n",
  49               readl(&crlapb_base->iou_switch_ctrl));
  50
  51         writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  52                (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  53                &crlapb_base->iou_switch_ctrl);
  54
  55         /* Global timer init - Program time stamp reference clk */
  56         val = readl(&crlapb_base->timestamp_ref_ctrl);
  57         val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  58         writel(val, &crlapb_base->timestamp_ref_ctrl);
  59
  60         debug("ref ctrl 0x%x\n",
  61               readl(&crlapb_base->timestamp_ref_ctrl));
  62
  63         /* Clear reset of timestamp reg */
  64         writel(0, &crlapb_base->rst_timestamp);
  65
  66         /*
  67          * Program freq register in System counter and
  68          * enable system counter.
  69          */
  70         writel(COUNTER_FREQUENCY,
  71                &iou_scntr_secure->base_frequency_id_register);
  72
  73         debug("counter val 0x%x\n",
  74               readl(&iou_scntr_secure->base_frequency_id_register));
  75
  76         writel(IOU_SCNTRS_CONTROL_EN,
  77                &iou_scntr_secure->counter_control_register);
  78
  79         debug("scntrs control 0x%x\n",
  80               readl(&iou_scntr_secure->counter_control_register));
  81         debug("timer 0x%llx\n", get_ticks());
  82         debug("timer 0x%llx\n", get_ticks());
  83
  84         return 0;
  85 }
  86
  87 static u8 versal_get_bootmode(void)
  88 {
  89         u8 bootmode;
  90         u32 reg = 0;
  91
  92         reg = readl(&crp_base->boot_mode_usr);
  93
  94         if (reg >> BOOT_MODE_ALT_SHIFT)
  95                 reg >>= BOOT_MODE_ALT_SHIFT;
  96
  97         bootmode = reg & BOOT_MODES_MASK;
  98
  99         return bootmode;
 100 }
 101
 102 int board_late_init(void)
 103 {
 104         u8 bootmode;
 105         struct udevice *dev;
 106         int bootseq = -1;
 107         int bootseq_len = 0;
 108         int env_targets_len = 0;
 109         const char *mode;
 110         char *new_targets;
 111         char *env_targets;
 112
 113         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 114                 debug("Saved variables - Skipping\n");
 115                 return 0;
 116         }
 117
 118         bootmode = versal_get_bootmode();
 119
 120         puts("Bootmode: ");
 121         switch (bootmode) {
 122         case USB_MODE:
 123                 puts("USB_MODE\n");
 124                 mode = "dfu_usb";
 125                 break;
 126         case JTAG_MODE:
 127                 puts("JTAG_MODE\n");
 128                 mode = "jtag pxe dhcp";
 129                 break;
 130         case QSPI_MODE_24BIT:
 131                 puts("QSPI_MODE_24\n");
 132                 mode = "xspi0";
 133                 break;
 134         case QSPI_MODE_32BIT:
 135                 puts("QSPI_MODE_32\n");
 136                 mode = "xspi0";
 137                 break;
 138         case OSPI_MODE:
 139                 puts("OSPI_MODE\n");
 140                 mode = "xspi0";
 141                 break;
 142         case EMMC_MODE:
 143                 puts("EMMC_MODE\n");
 144                 if (uclass_get_device_by_name(UCLASS_MMC,
 145                                               "sdhci@f1050000", &dev)) {
 146                         puts("Boot from EMMC but without SD1 enabled!\n");
 147                         return -1;
 148                 }
 149                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 150                 mode = "mmc";
 151                 bootseq = dev->seq;
 152                 break;
 153         case SD_MODE:
 154                 puts("SD_MODE\n");
 155                 if (uclass_get_device_by_name(UCLASS_MMC,
 156                                               "sdhci@f1040000", &dev)) {
 157                         puts("Boot from SD0 but without SD0 enabled!\n");
 158                         return -1;
 159                 }
 160                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 161
 162                 mode = "mmc";
 163                 bootseq = dev->seq;
 164                 break;
 165         case SD1_LSHFT_MODE:
 166                 puts("LVL_SHFT_");
 167                 /* fall through */
 168         case SD_MODE1:
 169                 puts("SD_MODE1\n");
 170                 if (uclass_get_device_by_name(UCLASS_MMC,
 171                                               "sdhci@f1050000", &dev)) {
 172                         puts("Boot from SD1 but without SD1 enabled!\n");
 173                         return -1;
 174                 }
 175                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 176
 177                 mode = "mmc";
 178                 bootseq = dev->seq;
 179                 break;
 180         default:
 181                 mode = "";
 182                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 183                 break;
 184         }
 185
 186         if (bootseq >= 0) {
 187                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 188                 debug("Bootseq len: %x\n", bootseq_len);
 189         }
 190
 191         /*
 192          * One terminating char + one byte for space between mode
 193          * and default boot_targets
 194          */
 195         env_targets = env_get("boot_targets");
 196         if (env_targets)
 197                 env_targets_len = strlen(env_targets);
 198
 199         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 200                              bootseq_len);
 201         if (!new_targets)
 202                 return -ENOMEM;
 203
 204         if (bootseq >= 0)
 205                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 206                         env_targets ? env_targets : "");
 207         else
 208                 sprintf(new_targets, "%s %s", mode,
 209                         env_targets ? env_targets : "");
 210
 211         env_set("boot_targets", new_targets);
 212
 213         return board_late_init_xilinx();
 214 }
 215
 216 int dram_init_banksize(void)
 217 {
 218         int ret;
 219
 220         ret = fdtdec_setup_memory_banksize();
 221         if (ret)
 222                 return ret;
 223
 224         mem_map_fill();
 225
 226         return 0;
 227 }
 228
 229 int dram_init(void)
 230 {
 231         if (fdtdec_setup_mem_size_base() != 0)
 232                 return -EINVAL;
 233
 234         return 0;
 235 }
 236
 237 void reset_cpu(ulong addr)
 238 {
 239 }