board/xilinx/versal/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2018 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <fdtdec.h>
   9 #include <malloc.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/hardware.h>
  12 #include <dm/device.h>
  13 #include <dm/uclass.h>
  14 #include <versalpl.h>
  15 #include <linux/sizes.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #if defined(CONFIG_FPGA_VERSALPL)
  20 static xilinx_desc versalpl = XILINX_VERSAL_DESC;
  21 #endif
  22
  23 int board_init(void)
  24 {
  25         printf("EL Level:\tEL%d\n", current_el());
  26
  27 #if defined(CONFIG_FPGA_VERSALPL)
  28         fpga_init();
  29         fpga_add(fpga_xilinx, &versalpl);
  30 #endif
  31
  32         return 0;
  33 }
  34
  35 int board_early_init_r(void)
  36 {
  37         u32 val;
  38
  39         if (current_el() != 3)
  40                 return 0;
  41
  42         debug("iou_switch ctrl div0 %x\n",
  43               readl(&crlapb_base->iou_switch_ctrl));
  44
  45         writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  46                (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  47                &crlapb_base->iou_switch_ctrl);
  48
  49         /* Global timer init - Program time stamp reference clk */
  50         val = readl(&crlapb_base->timestamp_ref_ctrl);
  51         val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  52         writel(val, &crlapb_base->timestamp_ref_ctrl);
  53
  54         debug("ref ctrl 0x%x\n",
  55               readl(&crlapb_base->timestamp_ref_ctrl));
  56
  57         /* Clear reset of timestamp reg */
  58         writel(0, &crlapb_base->rst_timestamp);
  59
  60         /*
  61          * Program freq register in System counter and
  62          * enable system counter.
  63          */
  64         writel(COUNTER_FREQUENCY,
  65                &iou_scntr_secure->base_frequency_id_register);
  66
  67         debug("counter val 0x%x\n",
  68               readl(&iou_scntr_secure->base_frequency_id_register));
  69
  70         writel(IOU_SCNTRS_CONTROL_EN,
  71                &iou_scntr_secure->counter_control_register);
  72
  73         debug("scntrs control 0x%x\n",
  74               readl(&iou_scntr_secure->counter_control_register));
  75         debug("timer 0x%llx\n", get_ticks());
  76         debug("timer 0x%llx\n", get_ticks());
  77
  78         return 0;
  79 }
  80
  81 int board_late_init(void)
  82 {
  83         u32 reg = 0;
  84         u8 bootmode;
  85         struct udevice *dev;
  86         int bootseq = -1;
  87         int bootseq_len = 0;
  88         int env_targets_len = 0;
  89         const char *mode;
  90         char *new_targets;
  91         char *env_targets;
  92         ulong initrd_hi;
  93
  94         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  95                 debug("Saved variables - Skipping\n");
  96                 return 0;
  97         }
  98
  99         reg = readl(&crp_base->boot_mode_usr);
 100
 101         if (reg >> BOOT_MODE_ALT_SHIFT)
 102                 reg >>= BOOT_MODE_ALT_SHIFT;
 103
 104         bootmode = reg & BOOT_MODES_MASK;
 105
 106         puts("Bootmode: ");
 107         switch (bootmode) {
 108         case JTAG_MODE:
 109                 puts("JTAG_MODE\n");
 110                 mode = "pxe dhcp";
 111                 break;
 112         case QSPI_MODE_24BIT:
 113                 puts("QSPI_MODE_24\n");
 114                 mode = "xspi0";
 115                 break;
 116         case QSPI_MODE_32BIT:
 117                 puts("QSPI_MODE_32\n");
 118                 mode = "xspi0";
 119                 break;
 120         case OSPI_MODE:
 121                 puts("OSPI_MODE\n");
 122                 mode = "xspi0";
 123                 break;
 124         case EMMC_MODE:
 125                 puts("EMMC_MODE\n");
 126                 mode = "mmc0";
 127                 break;
 128         case SD_MODE:
 129                 puts("SD_MODE\n");
 130                 if (uclass_get_device_by_name(UCLASS_MMC,
 131                                               "sdhci@f1040000", &dev)) {
 132                         puts("Boot from SD0 but without SD0 enabled!\n");
 133                         return -1;
 134                 }
 135                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 136
 137                 mode = "mmc";
 138                 bootseq = dev->seq;
 139                 break;
 140         case SD1_LSHFT_MODE:
 141                 puts("LVL_SHFT_");
 142                 /* fall through */
 143         case SD_MODE1:
 144                 puts("SD_MODE1\n");
 145                 if (uclass_get_device_by_name(UCLASS_MMC,
 146                                               "sdhci@f1050000", &dev)) {
 147                         puts("Boot from SD1 but without SD1 enabled!\n");
 148                         return -1;
 149                 }
 150                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 151
 152                 mode = "mmc";
 153                 bootseq = dev->seq;
 154                 break;
 155         default:
 156                 mode = "";
 157                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 158                 break;
 159         }
 160
 161         if (bootseq >= 0) {
 162                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 163                 debug("Bootseq len: %x\n", bootseq_len);
 164         }
 165
 166         /*
 167          * One terminating char + one byte for space between mode
 168          * and default boot_targets
 169          */
 170         env_targets = env_get("boot_targets");
 171         if (env_targets)
 172                 env_targets_len = strlen(env_targets);
 173
 174         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 175                              bootseq_len);
 176         if (!new_targets)
 177                 return -ENOMEM;
 178
 179         if (bootseq >= 0)
 180                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 181                         env_targets ? env_targets : "");
 182         else
 183                 sprintf(new_targets, "%s %s", mode,
 184                         env_targets ? env_targets : "");
 185
 186         env_set("boot_targets", new_targets);
 187
 188         initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
 189         initrd_hi = round_down(initrd_hi, SZ_16M);
 190         env_set_addr("initrd_high", (void *)initrd_hi);
 191
 192         return 0;
 193 }
 194
 195 int dram_init_banksize(void)
 196 {
 197         fdtdec_setup_memory_banksize();
 198
 199         return 0;
 200 }
 201
 202 int dram_init(void)
 203 {
 204         if (fdtdec_setup_mem_size_base() != 0)
 205                 return -EINVAL;
 206
 207         return 0;
 208 }
 209
 210 void reset_cpu(ulong addr)
 211 {
 212 }