board/xilinx/versal/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2018 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <fdtdec.h>
   9 #include <malloc.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/hardware.h>
  12 #include <dm/device.h>
  13 #include <dm/uclass.h>
  14 #include <versalpl.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 #if defined(CONFIG_FPGA_VERSALPL)
  19 static xilinx_desc versalpl = XILINX_VERSAL_DESC;
  20 #endif
  21
  22 int board_init(void)
  23 {
  24         printf("EL Level:\tEL%d\n", current_el());
  25
  26 #if defined(CONFIG_FPGA_VERSALPL)
  27         fpga_init();
  28         fpga_add(fpga_xilinx, &versalpl);
  29 #endif
  30
  31         return 0;
  32 }
  33
  34 int board_early_init_r(void)
  35 {
  36         u32 val;
  37
  38         if (current_el() != 3)
  39                 return 0;
  40
  41         debug("iou_switch ctrl div0 %x\n",
  42               readl(&crlapb_base->iou_switch_ctrl));
  43
  44         writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  45                (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  46                &crlapb_base->iou_switch_ctrl);
  47
  48         /* Global timer init - Program time stamp reference clk */
  49         val = readl(&crlapb_base->timestamp_ref_ctrl);
  50         val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  51         writel(val, &crlapb_base->timestamp_ref_ctrl);
  52
  53         debug("ref ctrl 0x%x\n",
  54               readl(&crlapb_base->timestamp_ref_ctrl));
  55
  56         /* Clear reset of timestamp reg */
  57         writel(0, &crlapb_base->rst_timestamp);
  58
  59         /*
  60          * Program freq register in System counter and
  61          * enable system counter.
  62          */
  63         writel(COUNTER_FREQUENCY,
  64                &iou_scntr_secure->base_frequency_id_register);
  65
  66         debug("counter val 0x%x\n",
  67               readl(&iou_scntr_secure->base_frequency_id_register));
  68
  69         writel(IOU_SCNTRS_CONTROL_EN,
  70                &iou_scntr_secure->counter_control_register);
  71
  72         debug("scntrs control 0x%x\n",
  73               readl(&iou_scntr_secure->counter_control_register));
  74         debug("timer 0x%llx\n", get_ticks());
  75         debug("timer 0x%llx\n", get_ticks());
  76
  77         return 0;
  78 }
  79
  80 int board_late_init(void)
  81 {
  82         u32 reg = 0;
  83         u8 bootmode;
  84         struct udevice *dev;
  85         int bootseq = -1;
  86         int bootseq_len = 0;
  87         int env_targets_len = 0;
  88         const char *mode;
  89         char *new_targets;
  90         char *env_targets;
  91
  92         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  93                 debug("Saved variables - Skipping\n");
  94                 return 0;
  95         }
  96
  97         reg = readl(&crp_base->boot_mode_usr);
  98
  99         if (reg >> BOOT_MODE_ALT_SHIFT)
 100                 reg >>= BOOT_MODE_ALT_SHIFT;
 101
 102         bootmode = reg & BOOT_MODES_MASK;
 103
 104         puts("Bootmode: ");
 105         switch (bootmode) {
 106         case JTAG_MODE:
 107                 puts("JTAG_MODE\n");
 108                 mode = "pxe dhcp";
 109                 break;
 110         case QSPI_MODE_24BIT:
 111                 puts("QSPI_MODE_24\n");
 112                 mode = "xspi0";
 113                 break;
 114         case QSPI_MODE_32BIT:
 115                 puts("QSPI_MODE_32\n");
 116                 mode = "xspi0";
 117                 break;
 118         case OSPI_MODE:
 119                 puts("OSPI_MODE\n");
 120                 mode = "xspi0";
 121                 break;
 122         case EMMC_MODE:
 123                 puts("EMMC_MODE\n");
 124                 mode = "mmc0";
 125                 break;
 126         case SD_MODE:
 127                 puts("SD_MODE\n");
 128                 if (uclass_get_device_by_name(UCLASS_MMC,
 129                                               "sdhci@f1040000", &dev)) {
 130                         puts("Boot from SD0 but without SD0 enabled!\n");
 131                         return -1;
 132                 }
 133                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 134
 135                 mode = "mmc";
 136                 bootseq = dev->seq;
 137                 break;
 138         case SD1_LSHFT_MODE:
 139                 puts("LVL_SHFT_");
 140                 /* fall through */
 141         case SD_MODE1:
 142                 puts("SD_MODE1\n");
 143                 if (uclass_get_device_by_name(UCLASS_MMC,
 144                                               "sdhci@f1050000", &dev)) {
 145                         puts("Boot from SD1 but without SD1 enabled!\n");
 146                         return -1;
 147                 }
 148                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 149
 150                 mode = "mmc";
 151                 bootseq = dev->seq;
 152                 break;
 153         default:
 154                 mode = "";
 155                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 156                 break;
 157         }
 158
 159         if (bootseq >= 0) {
 160                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 161                 debug("Bootseq len: %x\n", bootseq_len);
 162         }
 163
 164         /*
 165          * One terminating char + one byte for space between mode
 166          * and default boot_targets
 167          */
 168         env_targets = env_get("boot_targets");
 169         if (env_targets)
 170                 env_targets_len = strlen(env_targets);
 171
 172         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 173                              bootseq_len);
 174         if (!new_targets)
 175                 return -ENOMEM;
 176
 177         if (bootseq >= 0)
 178                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 179                         env_targets ? env_targets : "");
 180         else
 181                 sprintf(new_targets, "%s %s", mode,
 182                         env_targets ? env_targets : "");
 183
 184         env_set("boot_targets", new_targets);
 185
 186         return 0;
 187 }
 188
 189 int dram_init_banksize(void)
 190 {
 191         fdtdec_setup_memory_banksize();
 192
 193         return 0;
 194 }
 195
 196 int dram_init(void)
 197 {
 198         if (fdtdec_setup_mem_size_base() != 0)
 199                 return -EINVAL;
 200
 201         return 0;
 202 }
 203
 204 void reset_cpu(ulong addr)
 205 {
 206 }