board/xilinx/versal/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2018 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <fdtdec.h>
  10 #include <init.h>
  11 #include <malloc.h>
  12 #include <time.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <dm/device.h>
  17 #include <dm/uclass.h>
  18 #include <versalpl.h>
  19 #include "../common/board.h"
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #if defined(CONFIG_FPGA_VERSALPL)
  24 static xilinx_desc versalpl = XILINX_VERSAL_DESC;
  25 #endif
  26
  27 int board_init(void)
  28 {
  29         printf("EL Level:\tEL%d\n", current_el());
  30
  31 #if defined(CONFIG_FPGA_VERSALPL)
  32         fpga_init();
  33         fpga_add(fpga_xilinx, &versalpl);
  34 #endif
  35
  36         return 0;
  37 }
  38
  39 int board_early_init_r(void)
  40 {
  41         u32 val;
  42
  43         if (current_el() != 3)
  44                 return 0;
  45
  46         debug("iou_switch ctrl div0 %x\n",
  47               readl(&crlapb_base->iou_switch_ctrl));
  48
  49         writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  50                (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  51                &crlapb_base->iou_switch_ctrl);
  52
  53         /* Global timer init - Program time stamp reference clk */
  54         val = readl(&crlapb_base->timestamp_ref_ctrl);
  55         val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  56         writel(val, &crlapb_base->timestamp_ref_ctrl);
  57
  58         debug("ref ctrl 0x%x\n",
  59               readl(&crlapb_base->timestamp_ref_ctrl));
  60
  61         /* Clear reset of timestamp reg */
  62         writel(0, &crlapb_base->rst_timestamp);
  63
  64         /*
  65          * Program freq register in System counter and
  66          * enable system counter.
  67          */
  68         writel(COUNTER_FREQUENCY,
  69                &iou_scntr_secure->base_frequency_id_register);
  70
  71         debug("counter val 0x%x\n",
  72               readl(&iou_scntr_secure->base_frequency_id_register));
  73
  74         writel(IOU_SCNTRS_CONTROL_EN,
  75                &iou_scntr_secure->counter_control_register);
  76
  77         debug("scntrs control 0x%x\n",
  78               readl(&iou_scntr_secure->counter_control_register));
  79         debug("timer 0x%llx\n", get_ticks());
  80         debug("timer 0x%llx\n", get_ticks());
  81
  82         return 0;
  83 }
  84
  85 static u8 versal_get_bootmode(void)
  86 {
  87         u8 bootmode;
  88         u32 reg = 0;
  89
  90         reg = readl(&crp_base->boot_mode_usr);
  91
  92         if (reg >> BOOT_MODE_ALT_SHIFT)
  93                 reg >>= BOOT_MODE_ALT_SHIFT;
  94
  95         bootmode = reg & BOOT_MODES_MASK;
  96
  97         return bootmode;
  98 }
  99
 100 int board_late_init(void)
 101 {
 102         u8 bootmode;
 103         struct udevice *dev;
 104         int bootseq = -1;
 105         int bootseq_len = 0;
 106         int env_targets_len = 0;
 107         const char *mode;
 108         char *new_targets;
 109         char *env_targets;
 110
 111         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 112                 debug("Saved variables - Skipping\n");
 113                 return 0;
 114         }
 115
 116         bootmode = versal_get_bootmode();
 117
 118         puts("Bootmode: ");
 119         switch (bootmode) {
 120         case USB_MODE:
 121                 puts("USB_MODE\n");
 122                 mode = "dfu_usb";
 123                 break;
 124         case JTAG_MODE:
 125                 puts("JTAG_MODE\n");
 126                 mode = "jtag pxe dhcp";
 127                 break;
 128         case QSPI_MODE_24BIT:
 129                 puts("QSPI_MODE_24\n");
 130                 mode = "xspi0";
 131                 break;
 132         case QSPI_MODE_32BIT:
 133                 puts("QSPI_MODE_32\n");
 134                 mode = "xspi0";
 135                 break;
 136         case OSPI_MODE:
 137                 puts("OSPI_MODE\n");
 138                 mode = "xspi0";
 139                 break;
 140         case EMMC_MODE:
 141                 puts("EMMC_MODE\n");
 142                 if (uclass_get_device_by_name(UCLASS_MMC,
 143                                               "sdhci@f1050000", &dev)) {
 144                         puts("Boot from EMMC but without SD1 enabled!\n");
 145                         return -1;
 146                 }
 147                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 148                 mode = "mmc";
 149                 bootseq = dev->seq;
 150                 break;
 151         case SD_MODE:
 152                 puts("SD_MODE\n");
 153                 if (uclass_get_device_by_name(UCLASS_MMC,
 154                                               "sdhci@f1040000", &dev)) {
 155                         puts("Boot from SD0 but without SD0 enabled!\n");
 156                         return -1;
 157                 }
 158                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 159
 160                 mode = "mmc";
 161                 bootseq = dev->seq;
 162                 break;
 163         case SD1_LSHFT_MODE:
 164                 puts("LVL_SHFT_");
 165                 /* fall through */
 166         case SD_MODE1:
 167                 puts("SD_MODE1\n");
 168                 if (uclass_get_device_by_name(UCLASS_MMC,
 169                                               "sdhci@f1050000", &dev)) {
 170                         puts("Boot from SD1 but without SD1 enabled!\n");
 171                         return -1;
 172                 }
 173                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 174
 175                 mode = "mmc";
 176                 bootseq = dev->seq;
 177                 break;
 178         default:
 179                 mode = "";
 180                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 181                 break;
 182         }
 183
 184         if (bootseq >= 0) {
 185                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 186                 debug("Bootseq len: %x\n", bootseq_len);
 187         }
 188
 189         /*
 190          * One terminating char + one byte for space between mode
 191          * and default boot_targets
 192          */
 193         env_targets = env_get("boot_targets");
 194         if (env_targets)
 195                 env_targets_len = strlen(env_targets);
 196
 197         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 198                              bootseq_len);
 199         if (!new_targets)
 200                 return -ENOMEM;
 201
 202         if (bootseq >= 0)
 203                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 204                         env_targets ? env_targets : "");
 205         else
 206                 sprintf(new_targets, "%s %s", mode,
 207                         env_targets ? env_targets : "");
 208
 209         env_set("boot_targets", new_targets);
 210
 211         return board_late_init_xilinx();
 212 }
 213
 214 int dram_init_banksize(void)
 215 {
 216         int ret;
 217
 218         ret = fdtdec_setup_memory_banksize();
 219         if (ret)
 220                 return ret;
 221
 222         mem_map_fill();
 223
 224         return 0;
 225 }
 226
 227 int dram_init(void)
 228 {
 229         if (fdtdec_setup_mem_size_base() != 0)
 230                 return -EINVAL;
 231
 232         return 0;
 233 }
 234
 235 void reset_cpu(ulong addr)
 236 {
 237 }