board/xilinx/versal/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2018 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <env.h>
  10 #include <fdtdec.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <malloc.h>
  14 #include <time.h>
  15 #include <asm/cache.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <dm/device.h>
  20 #include <dm/uclass.h>
  21 #include <versalpl.h>
  22 #include "../common/board.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #if defined(CONFIG_FPGA_VERSALPL)
  27 static xilinx_desc versalpl = XILINX_VERSAL_DESC;
  28 #endif
  29
  30 int board_init(void)
  31 {
  32         printf("EL Level:\tEL%d\n", current_el());
  33
  34 #if defined(CONFIG_FPGA_VERSALPL)
  35         fpga_init();
  36         fpga_add(fpga_xilinx, &versalpl);
  37 #endif
  38
  39         return 0;
  40 }
  41
  42 int board_early_init_r(void)
  43 {
  44         u32 val;
  45
  46         if (current_el() != 3)
  47                 return 0;
  48
  49         debug("iou_switch ctrl div0 %x\n",
  50               readl(&crlapb_base->iou_switch_ctrl));
  51
  52         writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  53                (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  54                &crlapb_base->iou_switch_ctrl);
  55
  56         /* Global timer init - Program time stamp reference clk */
  57         val = readl(&crlapb_base->timestamp_ref_ctrl);
  58         val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  59         writel(val, &crlapb_base->timestamp_ref_ctrl);
  60
  61         debug("ref ctrl 0x%x\n",
  62               readl(&crlapb_base->timestamp_ref_ctrl));
  63
  64         /* Clear reset of timestamp reg */
  65         writel(0, &crlapb_base->rst_timestamp);
  66
  67         /*
  68          * Program freq register in System counter and
  69          * enable system counter.
  70          */
  71         writel(COUNTER_FREQUENCY,
  72                &iou_scntr_secure->base_frequency_id_register);
  73
  74         debug("counter val 0x%x\n",
  75               readl(&iou_scntr_secure->base_frequency_id_register));
  76
  77         writel(IOU_SCNTRS_CONTROL_EN,
  78                &iou_scntr_secure->counter_control_register);
  79
  80         debug("scntrs control 0x%x\n",
  81               readl(&iou_scntr_secure->counter_control_register));
  82         debug("timer 0x%llx\n", get_ticks());
  83         debug("timer 0x%llx\n", get_ticks());
  84
  85         return 0;
  86 }
  87
  88 static u8 versal_get_bootmode(void)
  89 {
  90         u8 bootmode;
  91         u32 reg = 0;
  92
  93         reg = readl(&crp_base->boot_mode_usr);
  94
  95         if (reg >> BOOT_MODE_ALT_SHIFT)
  96                 reg >>= BOOT_MODE_ALT_SHIFT;
  97
  98         bootmode = reg & BOOT_MODES_MASK;
  99
 100         return bootmode;
 101 }
 102
 103 int board_late_init(void)
 104 {
 105         u8 bootmode;
 106         struct udevice *dev;
 107         int bootseq = -1;
 108         int bootseq_len = 0;
 109         int env_targets_len = 0;
 110         const char *mode;
 111         char *new_targets;
 112         char *env_targets;
 113
 114         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 115                 debug("Saved variables - Skipping\n");
 116                 return 0;
 117         }
 118
 119         bootmode = versal_get_bootmode();
 120
 121         puts("Bootmode: ");
 122         switch (bootmode) {
 123         case USB_MODE:
 124                 puts("USB_MODE\n");
 125                 mode = "dfu_usb";
 126                 break;
 127         case JTAG_MODE:
 128                 puts("JTAG_MODE\n");
 129                 mode = "jtag pxe dhcp";
 130                 break;
 131         case QSPI_MODE_24BIT:
 132                 puts("QSPI_MODE_24\n");
 133                 mode = "xspi0";
 134                 break;
 135         case QSPI_MODE_32BIT:
 136                 puts("QSPI_MODE_32\n");
 137                 mode = "xspi0";
 138                 break;
 139         case OSPI_MODE:
 140                 puts("OSPI_MODE\n");
 141                 mode = "xspi0";
 142                 break;
 143         case EMMC_MODE:
 144                 puts("EMMC_MODE\n");
 145                 if (uclass_get_device_by_name(UCLASS_MMC,
 146                                               "sdhci@f1050000", &dev)) {
 147                         puts("Boot from EMMC but without SD1 enabled!\n");
 148                         return -1;
 149                 }
 150                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 151                 mode = "mmc";
 152                 bootseq = dev->seq;
 153                 break;
 154         case SD_MODE:
 155                 puts("SD_MODE\n");
 156                 if (uclass_get_device_by_name(UCLASS_MMC,
 157                                               "sdhci@f1040000", &dev)) {
 158                         puts("Boot from SD0 but without SD0 enabled!\n");
 159                         return -1;
 160                 }
 161                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 162
 163                 mode = "mmc";
 164                 bootseq = dev->seq;
 165                 break;
 166         case SD1_LSHFT_MODE:
 167                 puts("LVL_SHFT_");
 168                 /* fall through */
 169         case SD_MODE1:
 170                 puts("SD_MODE1\n");
 171                 if (uclass_get_device_by_name(UCLASS_MMC,
 172                                               "sdhci@f1050000", &dev)) {
 173                         puts("Boot from SD1 but without SD1 enabled!\n");
 174                         return -1;
 175                 }
 176                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 177
 178                 mode = "mmc";
 179                 bootseq = dev->seq;
 180                 break;
 181         default:
 182                 mode = "";
 183                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 184                 break;
 185         }
 186
 187         if (bootseq >= 0) {
 188                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 189                 debug("Bootseq len: %x\n", bootseq_len);
 190         }
 191
 192         /*
 193          * One terminating char + one byte for space between mode
 194          * and default boot_targets
 195          */
 196         env_targets = env_get("boot_targets");
 197         if (env_targets)
 198                 env_targets_len = strlen(env_targets);
 199
 200         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 201                              bootseq_len);
 202         if (!new_targets)
 203                 return -ENOMEM;
 204
 205         if (bootseq >= 0)
 206                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 207                         env_targets ? env_targets : "");
 208         else
 209                 sprintf(new_targets, "%s %s", mode,
 210                         env_targets ? env_targets : "");
 211
 212         env_set("boot_targets", new_targets);
 213
 214         return board_late_init_xilinx();
 215 }
 216
 217 int dram_init_banksize(void)
 218 {
 219         int ret;
 220
 221         ret = fdtdec_setup_memory_banksize();
 222         if (ret)
 223                 return ret;
 224
 225         mem_map_fill();
 226
 227         return 0;
 228 }
 229
 230 int dram_init(void)
 231 {
 232         if (fdtdec_setup_mem_size_base() != 0)
 233                 return -EINVAL;
 234
 235         return 0;
 236 }
 237
 238 void reset_cpu(ulong addr)
 239 {
 240 }