1 if TARGET_MICROBLAZE_GENERIC
4 default "microblaze-generic"
10 string "Board configuration name"
11 default "microblaze-generic"
13 This option contains information about board configuration name.
14 Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
15 will be used for board configuration.
17 config XILINX_MICROBLAZE0_USE_MSR_INSTR
18 int "USE_MSR_INSTR range (0:1)"
21 config XILINX_MICROBLAZE0_USE_PCMP_INSTR
22 int "USE_PCMP_INSTR range (0:1)"
25 config XILINX_MICROBLAZE0_USE_BARREL
26 int "USE_BARREL range (0:1)"
29 config XILINX_MICROBLAZE0_USE_DIV
30 int "USE_DIV range (0:1)"
33 config XILINX_MICROBLAZE0_USE_HW_MUL
34 int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
37 config XILINX_MICROBLAZE0_HW_VER
38 string "Core version number"
41 config XILINX_MICROBLAZE0_FPGA_FAMILY
42 string "Targeted FPGA family"
45 This option contains info about the target FPGA architecture
46 (Zynq-7000, UltraScale+ Kintex, etc) that the MicroBlaze soft core is
47 implemented on. It corresponds to the C_FAMILY hdl parameter.
49 config XILINX_MICROBLAZE0_USR_EXCEP
50 bool "MicroBlaze user exception support"
53 Enable this option in order to install the user exception handler
54 (_exception_handler routine from arch/microblaze/cpu/exception.c) in
55 the exception vector table. The user exception vector is located at
56 C_BASE_VECTORS + 0x8 address.
58 config XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP
59 bool "MicroBlaze delay slot exception support"
62 Enable this option if the MicroBlaze processor supports exceptions
63 caused by delay slot instructions (processor version >= v5.00). When
64 enabled, the hw exception handler will print a message indicating
65 whether the exception was triggered by a delay slot instruction.
67 config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
68 hex "Location of MicroBlaze vectors"
71 Memory address location of the exception vector table. It is
72 configurable via the C_BASE_VECTORS hdl parameter.
74 config XILINX_MICROBLAZE0_USE_WDC
75 bool "MicroBlaze wdc instruction support"
78 Enable this option if the MicroBlaze processor is configured with
79 support for the "wdc" (Write to Data Cache) instruction.
81 config SPL_XILINX_MICROBLAZE0_USE_WDC
83 default XILINX_MICROBLAZE0_USE_WDC
85 config XILINX_MICROBLAZE0_USE_WIC
86 bool "MicroBlaze wic instruction support"
89 Enable this option if the MicroBlaze processor is configured with
90 support for the "wic" (Write to Instruction Cache) instruction.
92 config SPL_XILINX_MICROBLAZE0_USE_WIC
94 default XILINX_MICROBLAZE0_USE_WIC
96 config XILINX_MICROBLAZE0_DCACHE_SIZE
97 int "Default data cache size"
100 This fallback size will be used when no dcache info can be found in
101 the device tree, or when the data cache is flushed very early in the
102 boot process, before device tree is available.
104 config XILINX_MICROBLAZE0_ICACHE_SIZE
105 int "Default instruction cache size"
108 This fallback size will be used when no icache info can be found in
109 the device tree, or when the instruction cache is flushed very early
110 in the boot process, before device tree is available.
112 config XILINX_MICROBLAZE0_PVR
113 bool "MicroBlaze PVR support"
115 Enables helper functions and macros needed to manipulate PVR
116 (Processor Version Register) data. Currently, only the microblaze
117 UCLASS_CPU driver makes use of this feature to retrieve CPU info at