board/xes/xpedite520x/ddr.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <i2c.h>
  11
  12 #include <asm/fsl_ddr_sdram.h>
  13 #include <asm/fsl_ddr_dimm_params.h>
  14
  15 static void
  16 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
  17 {
  18         i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
  19
  20         /* We use soldered memory, but use an SPD EEPROM to describe it.
  21          * The SPD has an unspecified dimm type, but the DDR2 initialization
  22          * code requires a specific type to be specified. This sets the type
  23          * as a standard unregistered SO-DIMM. */
  24         if (spd->dimm_type == 0) {
  25                 spd->dimm_type = 0x4;
  26                 ((uchar *)spd)[63] += 0x4;
  27         }
  28 }
  29
  30 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
  31                         unsigned int ctrl_num)
  32 {
  33         unsigned int i;
  34
  35         if (ctrl_num) {
  36                 printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
  37                 return;
  38         }
  39
  40         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
  41                 get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
  42 }
  43
  44 void fsl_ddr_board_options(memctl_options_t *popts,
  45                                 dimm_params_t *pdimm,
  46                                 unsigned int ctrl_num)
  47 {
  48         /*
  49          * Factors to consider for clock adjust:
  50          *      - number of chips on bus
  51          *      - position of slot
  52          *      - DDR1 vs. DDR2?
  53          *      - ???
  54          *
  55          * This needs to be determined on a board-by-board basis.
  56          *      0110    3/4 cycle late
  57          *      0111    7/8 cycle late
  58          */
  59         popts->clk_adjust = 7;
  60
  61         /*
  62          * Factors to consider for CPO:
  63          *      - frequency
  64          *      - ddr1 vs. ddr2
  65          */
  66         popts->cpo_override = 9;
  67
  68         /*
  69          * Factors to consider for write data delay:
  70          *      - number of DIMMs
  71          *
  72          * 1 = 1/4 clock delay
  73          * 2 = 1/2 clock delay
  74          * 3 = 3/4 clock delay
  75          * 4 = 1   clock delay
  76          * 5 = 5/4 clock delay
  77          * 6 = 3/2 clock delay
  78          */
  79         popts->write_data_delay = 3;
  80
  81         /*
  82          * Factors to consider for half-strength driver enable:
  83          *      - number of DIMMs installed
  84          */
  85         popts->half_strength_driver_enable = 0;
  86 }