2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/immap_85xx.h>
27 #include <asm/fsl_pci.h>
29 #include <fdt_support.h>
31 int first_free_busno = 0;
34 static struct pci_controller pci1_hose;
37 static struct pci_controller pcie1_hose;
40 static struct pci_controller pcie2_hose;
43 static struct pci_controller pcie3_hose;
47 /* Correlate host/agent POR bits to usable info. Table 4-14 */
48 struct host_agent_cfg_t {
51 } host_agent_cfg[8] = {
62 /* Correlate port width POR bits to usable info. Table 4-15 */
63 struct io_port_cfg_t {
84 #elif defined CONFIG_MPC8548
85 /* Correlate host/agent POR bits to usable info. Table 4-12 */
86 struct host_agent_cfg_t {
90 } host_agent_cfg[8] = {
94 {{0, 0}, {0}, 0}, /* reserved */
101 /* Correlate port width POR bits to usable info. Table 4-13 */
102 struct io_port_cfg_t {
117 void pci_init_board(void)
119 struct pci_controller *hose;
120 volatile ccsr_fsl_pci_t *pci;
123 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
124 uint devdisr = gur->devdisr;
125 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
126 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
127 struct pci_region *r;
130 uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD);
131 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
132 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
133 uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1;
134 uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
136 width = 0; /* Silence compiler warning... */
137 io_sel &= 0xf; /* Silence compiler warning... */
138 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
140 host = host_agent_cfg[host_agent].pci_host[0];
144 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
145 printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
147 pcix ? "PCIX" : "PCI",
148 pci_spd_norm ? ">=" : "<=",
149 pcix ? freq * 2 : freq,
150 host ? "host" : "agent",
151 pci_arb ? "arbiter" : "external-arbiter");
154 r += fsl_pci_setup_inbound_windows(r);
156 /* outbound memory */
158 CONFIG_SYS_PCI1_MEM_BASE,
159 CONFIG_SYS_PCI1_MEM_PHYS,
160 CONFIG_SYS_PCI1_MEM_SIZE,
165 CONFIG_SYS_PCI1_IO_BASE,
166 CONFIG_SYS_PCI1_IO_PHYS,
167 CONFIG_SYS_PCI1_IO_SIZE,
170 hose->region_count = r - hose->regions;
172 hose->first_busno = first_free_busno;
173 pci_setup_indirect(hose, (int)&pci->cfg_addr,
174 (int)&pci->cfg_data);
178 /* Unlock inbound PCI configuration cycles */
180 fsl_pci_config_unlock(hose);
182 first_free_busno = hose->last_busno + 1;
183 printf(" PCI1 on bus %02x - %02x\n",
184 hose->first_busno, hose->last_busno);
186 printf(" PCI1: disabled\n");
188 #elif defined CONFIG_MPC8548
189 /* PCI1 not present on MPC8572 */
190 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
193 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
195 host = host_agent_cfg[host_agent].pcie_root[0];
196 width = io_port_cfg[io_sel].pcie_width[0];
199 if (width && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
200 printf("\n PCIE1 connected as %s (x%d)",
201 host ? "Root Complex" : "End Point", width);
202 if (pci->pme_msg_det) {
203 pci->pme_msg_det = 0xffffffff;
204 debug(" with errors. Clearing. Now 0x%08x",
210 r += fsl_pci_setup_inbound_windows(r);
212 /* outbound memory */
214 CONFIG_SYS_PCIE1_MEM_BASE,
215 CONFIG_SYS_PCIE1_MEM_PHYS,
216 CONFIG_SYS_PCIE1_MEM_SIZE,
221 CONFIG_SYS_PCIE1_IO_BASE,
222 CONFIG_SYS_PCIE1_IO_PHYS,
223 CONFIG_SYS_PCIE1_IO_SIZE,
226 hose->region_count = r - hose->regions;
228 hose->first_busno = first_free_busno;
229 pci_setup_indirect(hose, (int)&pci->cfg_addr,
230 (int) &pci->cfg_data);
234 /* Unlock inbound PCI configuration cycles */
236 fsl_pci_config_unlock(hose);
238 first_free_busno = hose->last_busno + 1;
239 printf(" PCIE1 on bus %02x - %02x\n",
240 hose->first_busno, hose->last_busno);
243 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
244 #endif /* CONFIG_PCIE1 */
247 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
249 host = host_agent_cfg[host_agent].pcie_root[1];
250 width = io_port_cfg[io_sel].pcie_width[1];
253 if (width && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
254 printf("\n PCIE2 connected as %s (x%d)",
255 host ? "Root Complex" : "End Point", width);
256 if (pci->pme_msg_det) {
257 pci->pme_msg_det = 0xffffffff;
258 debug(" with errors. Clearing. Now 0x%08x",
264 r += fsl_pci_setup_inbound_windows(r);
266 /* outbound memory */
268 CONFIG_SYS_PCIE2_MEM_BASE,
269 CONFIG_SYS_PCIE2_MEM_PHYS,
270 CONFIG_SYS_PCIE2_MEM_SIZE,
275 CONFIG_SYS_PCIE2_IO_BASE,
276 CONFIG_SYS_PCIE2_IO_PHYS,
277 CONFIG_SYS_PCIE2_IO_SIZE,
280 hose->region_count = r - hose->regions;
282 hose->first_busno = first_free_busno;
283 pci_setup_indirect(hose, (int)&pci->cfg_addr,
284 (int)&pci->cfg_data);
288 /* Unlock inbound PCI configuration cycles */
290 fsl_pci_config_unlock(hose);
292 first_free_busno = hose->last_busno + 1;
293 printf(" PCIE2 on bus %02x - %02x\n",
294 hose->first_busno, hose->last_busno);
297 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
298 #endif /* CONFIG_PCIE2 */
301 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
303 host = host_agent_cfg[host_agent].pcie_root[2];
304 width = io_port_cfg[io_sel].pcie_width[2];
307 if (width && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
308 printf("\n PCIE3 connected as %s (x%d)",
309 host ? "Root Complex" : "End Point", width);
310 if (pci->pme_msg_det) {
311 pci->pme_msg_det = 0xffffffff;
312 debug(" with errors. Clearing. Now 0x%08x",
318 r += fsl_pci_setup_inbound_windows(r);
320 /* outbound memory */
322 CONFIG_SYS_PCIE3_MEM_BASE,
323 CONFIG_SYS_PCIE3_MEM_PHYS,
324 CONFIG_SYS_PCIE3_MEM_SIZE,
329 CONFIG_SYS_PCIE3_IO_BASE,
330 CONFIG_SYS_PCIE3_IO_PHYS,
331 CONFIG_SYS_PCIE3_IO_SIZE,
334 hose->region_count = r - hose->regions;
336 hose->first_busno = first_free_busno;
337 pci_setup_indirect(hose, (int)&pci->cfg_addr,
338 (int)&pci->cfg_data);
342 /* Unlock inbound PCI configuration cycles */
344 fsl_pci_config_unlock(hose);
346 first_free_busno = hose->last_busno + 1;
347 printf(" PCIE3 on bus %02x - %02x\n",
348 hose->first_busno, hose->last_busno);
351 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
352 #endif /* CONFIG_PCIE3 */
355 #if defined(CONFIG_OF_BOARD_SETUP)
356 void ft_board_pci_setup(void *blob, bd_t *bd)
358 /* TODO - make node name (eg pci0) dynamic */
360 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
363 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
366 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
369 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
372 #endif /* CONFIG_OF_BOARD_SETUP */