board/xes/common/fsl_85xx_pci.c

   1 /*
   2  * Copyright 2008 Extreme Engineering Solutions, Inc.
   3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <pci.h>
  26 #include <asm/immap_85xx.h>
  27 #include <asm/fsl_pci.h>
  28 #include <libfdt.h>
  29 #include <fdt_support.h>
  30
  31 int first_free_busno = 0;
  32
  33 #ifdef CONFIG_PCI1
  34 static struct pci_controller pci1_hose;
  35 #endif
  36 #ifdef CONFIG_PCIE1
  37 static struct pci_controller pcie1_hose;
  38 #endif
  39 #ifdef CONFIG_PCIE2
  40 static struct pci_controller pcie2_hose;
  41 #endif
  42 #ifdef CONFIG_PCIE3
  43 static struct pci_controller pcie3_hose;
  44 #endif
  45
  46 #ifdef CONFIG_MPC8572
  47 /* Correlate host/agent POR bits to usable info. Table 4-14 */
  48 struct host_agent_cfg_t {
  49         uchar pcie_root[3];
  50         uchar rio_host;
  51 } host_agent_cfg[8] = {
  52         {{0, 0, 0}, 0},
  53         {{0, 1, 1}, 1},
  54         {{1, 0, 1}, 0},
  55         {{1, 1, 0}, 1},
  56         {{0, 0, 1}, 0},
  57         {{0, 1, 0}, 1},
  58         {{1, 0, 0}, 0},
  59         {{1, 1, 1}, 1}
  60 };
  61
  62 /* Correlate port width POR bits to usable info. Table 4-15 */
  63 struct io_port_cfg_t {
  64         uchar pcie_width[3];
  65         uchar rio_width;
  66 } io_port_cfg[16] = {
  67         {{0, 0, 0}, 0},
  68         {{0, 0, 0}, 0},
  69         {{4, 0, 0}, 0},
  70         {{4, 4, 0}, 0},
  71         {{0, 0, 0}, 0},
  72         {{0, 0, 0}, 0},
  73         {{0, 0, 0}, 4},
  74         {{4, 2, 2}, 0},
  75         {{0, 0, 0}, 0},
  76         {{0, 0, 0}, 0},
  77         {{0, 0, 0}, 0},
  78         {{4, 0, 0}, 4},
  79         {{4, 0, 0}, 4},
  80         {{0, 0, 0}, 4},
  81         {{0, 0, 0}, 4},
  82         {{8, 0, 0}, 0},
  83 };
  84 #elif defined CONFIG_MPC8548
  85 /* Correlate host/agent POR bits to usable info. Table 4-12 */
  86 struct host_agent_cfg_t {
  87         uchar pci_host[2];
  88         uchar pcie_root[1];
  89         uchar rio_host;
  90 } host_agent_cfg[8] = {
  91         {{1, 1}, {0}, 0},
  92         {{1, 1}, {1}, 0},
  93         {{1, 1}, {0}, 1},
  94         {{0, 0}, {0}, 0}, /* reserved */
  95         {{0, 1}, {1}, 0},
  96         {{1, 1}, {1}, 0},
  97         {{0, 1}, {1}, 1},
  98         {{1, 1}, {1}, 1}
  99 };
 100
 101 /* Correlate port width POR bits to usable info. Table 4-13 */
 102 struct io_port_cfg_t {
 103         uchar pcie_width[1];
 104         uchar rio_width;
 105 } io_port_cfg[8] = {
 106         {{0}, 0},
 107         {{0}, 0},
 108         {{0}, 0},
 109         {{4}, 4},
 110         {{4}, 4},
 111         {{0}, 4},
 112         {{0}, 4},
 113         {{8}, 0},
 114 };
 115 #endif
 116
 117 void pci_init_board(void)
 118 {
 119         struct pci_controller *hose;
 120         volatile ccsr_fsl_pci_t *pci;
 121         int width;
 122         int host;
 123         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 124         uint devdisr = gur->devdisr;
 125         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 126         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 127         struct pci_region *r;
 128
 129 #ifdef CONFIG_PCI1
 130         uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD);
 131         uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
 132         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 133         uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1;
 134         uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
 135
 136         width = 0; /* Silence compiler warning... */
 137         io_sel &= 0xf; /* Silence compiler warning... */
 138         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 139         hose = &pci1_hose;
 140         host = host_agent_cfg[host_agent].pci_host[0];
 141         r = hose->regions;
 142
 143
 144         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 145                 printf("\n    PCI1: %d bit %s, %s %d MHz, %s, %s\n",
 146                         pci_32 ? 32 : 64,
 147                         pcix ? "PCIX" : "PCI",
 148                         pci_spd_norm ?  ">=" : "<=",
 149                         pcix ? freq * 2 : freq,
 150                         host ? "host" : "agent",
 151                         pci_arb ? "arbiter" : "external-arbiter");
 152
 153                 /* inbound */
 154                 r += fsl_pci_setup_inbound_windows(r);
 155
 156                 /* outbound memory */
 157                 pci_set_region(r++,
 158                                 CONFIG_SYS_PCI1_MEM_BASE,
 159                                 CONFIG_SYS_PCI1_MEM_PHYS,
 160                                 CONFIG_SYS_PCI1_MEM_SIZE,
 161                                 PCI_REGION_MEM);
 162
 163                 /* outbound io */
 164                 pci_set_region(r++,
 165                                 CONFIG_SYS_PCI1_IO_BASE,
 166                                 CONFIG_SYS_PCI1_IO_PHYS,
 167                                 CONFIG_SYS_PCI1_IO_SIZE,
 168                                 PCI_REGION_IO);
 169
 170                 hose->region_count = r - hose->regions;
 171
 172                 hose->first_busno = first_free_busno;
 173                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 174                                    (int)&pci->cfg_data);
 175
 176                 fsl_pci_init(hose);
 177
 178                 /* Unlock inbound PCI configuration cycles */
 179                 if (!host)
 180                         fsl_pci_config_unlock(hose);
 181
 182                 first_free_busno = hose->last_busno + 1;
 183                 printf("    PCI1 on bus %02x - %02x\n",
 184                         hose->first_busno, hose->last_busno);
 185         } else {
 186                 printf("    PCI1: disabled\n");
 187         }
 188 #elif defined CONFIG_MPC8548
 189         /* PCI1 not present on MPC8572 */
 190         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 191 #endif
 192 #ifdef CONFIG_PCIE1
 193         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 194         hose = &pcie1_hose;
 195         host = host_agent_cfg[host_agent].pcie_root[0];
 196         width = io_port_cfg[io_sel].pcie_width[0];
 197         r = hose->regions;
 198
 199         if (width && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
 200                 printf("\n    PCIE1 connected as %s (x%d)",
 201                         host ? "Root Complex" : "End Point", width);
 202                 if (pci->pme_msg_det) {
 203                         pci->pme_msg_det = 0xffffffff;
 204                         debug(" with errors.  Clearing.  Now 0x%08x",
 205                                 pci->pme_msg_det);
 206                 }
 207                 printf("\n");
 208
 209                 /* inbound */
 210                 r += fsl_pci_setup_inbound_windows(r);
 211
 212                 /* outbound memory */
 213                 pci_set_region(r++,
 214                                 CONFIG_SYS_PCIE1_MEM_BASE,
 215                                 CONFIG_SYS_PCIE1_MEM_PHYS,
 216                                 CONFIG_SYS_PCIE1_MEM_SIZE,
 217                                 PCI_REGION_MEM);
 218
 219                 /* outbound io */
 220                 pci_set_region(r++,
 221                                 CONFIG_SYS_PCIE1_IO_BASE,
 222                                 CONFIG_SYS_PCIE1_IO_PHYS,
 223                                 CONFIG_SYS_PCIE1_IO_SIZE,
 224                                 PCI_REGION_IO);
 225
 226                 hose->region_count = r - hose->regions;
 227
 228                 hose->first_busno = first_free_busno;
 229                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 230                                         (int) &pci->cfg_data);
 231
 232                 fsl_pci_init(hose);
 233
 234                 /* Unlock inbound PCI configuration cycles */
 235                 if (!host)
 236                         fsl_pci_config_unlock(hose);
 237
 238                 first_free_busno = hose->last_busno + 1;
 239                 printf("    PCIE1 on bus %02x - %02x\n",
 240                                 hose->first_busno, hose->last_busno);
 241         }
 242 #else
 243         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 244 #endif /* CONFIG_PCIE1 */
 245
 246 #ifdef CONFIG_PCIE2
 247         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 248         hose = &pcie2_hose;
 249         host = host_agent_cfg[host_agent].pcie_root[1];
 250         width = io_port_cfg[io_sel].pcie_width[1];
 251         r = hose->regions;
 252
 253         if (width && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
 254                 printf("\n    PCIE2 connected as %s (x%d)",
 255                         host ? "Root Complex" : "End Point", width);
 256                 if (pci->pme_msg_det) {
 257                         pci->pme_msg_det = 0xffffffff;
 258                         debug(" with errors.  Clearing.  Now 0x%08x",
 259                                 pci->pme_msg_det);
 260                 }
 261                 printf("\n");
 262
 263                 /* inbound */
 264                 r += fsl_pci_setup_inbound_windows(r);
 265
 266                 /* outbound memory */
 267                 pci_set_region(r++,
 268                                 CONFIG_SYS_PCIE2_MEM_BASE,
 269                                 CONFIG_SYS_PCIE2_MEM_PHYS,
 270                                 CONFIG_SYS_PCIE2_MEM_SIZE,
 271                                 PCI_REGION_MEM);
 272
 273                 /* outbound io */
 274                 pci_set_region(r++,
 275                                 CONFIG_SYS_PCIE2_IO_BASE,
 276                                 CONFIG_SYS_PCIE2_IO_PHYS,
 277                                 CONFIG_SYS_PCIE2_IO_SIZE,
 278                                 PCI_REGION_IO);
 279
 280                 hose->region_count = r - hose->regions;
 281
 282                 hose->first_busno = first_free_busno;
 283                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 284                                         (int)&pci->cfg_data);
 285
 286                 fsl_pci_init(hose);
 287
 288                 /* Unlock inbound PCI configuration cycles */
 289                 if (!host)
 290                         fsl_pci_config_unlock(hose);
 291
 292                 first_free_busno = hose->last_busno + 1;
 293                 printf("    PCIE2 on bus %02x - %02x\n",
 294                                 hose->first_busno, hose->last_busno);
 295         }
 296 #else
 297         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 298 #endif /* CONFIG_PCIE2 */
 299
 300 #ifdef CONFIG_PCIE3
 301         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 302         hose = &pcie3_hose;
 303         host = host_agent_cfg[host_agent].pcie_root[2];
 304         width = io_port_cfg[io_sel].pcie_width[2];
 305         r = hose->regions;
 306
 307         if (width && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
 308                 printf("\n    PCIE3 connected as %s (x%d)",
 309                         host ? "Root Complex" : "End Point", width);
 310                 if (pci->pme_msg_det) {
 311                         pci->pme_msg_det = 0xffffffff;
 312                         debug(" with errors.  Clearing.  Now 0x%08x",
 313                                 pci->pme_msg_det);
 314                 }
 315                 printf("\n");
 316
 317                 /* inbound */
 318                 r += fsl_pci_setup_inbound_windows(r);
 319
 320                 /* outbound memory */
 321                 pci_set_region(r++,
 322                                 CONFIG_SYS_PCIE3_MEM_BASE,
 323                                 CONFIG_SYS_PCIE3_MEM_PHYS,
 324                                 CONFIG_SYS_PCIE3_MEM_SIZE,
 325                                 PCI_REGION_MEM);
 326
 327                 /* outbound io */
 328                 pci_set_region(r++,
 329                                 CONFIG_SYS_PCIE3_IO_BASE,
 330                                 CONFIG_SYS_PCIE3_IO_PHYS,
 331                                 CONFIG_SYS_PCIE3_IO_SIZE,
 332                                 PCI_REGION_IO);
 333
 334                 hose->region_count = r - hose->regions;
 335
 336                 hose->first_busno = first_free_busno;
 337                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 338                                         (int)&pci->cfg_data);
 339
 340                 fsl_pci_init(hose);
 341
 342                 /* Unlock inbound PCI configuration cycles */
 343                 if (!host)
 344                         fsl_pci_config_unlock(hose);
 345
 346                 first_free_busno = hose->last_busno + 1;
 347                 printf("    PCIE3 on bus %02x - %02x\n",
 348                                 hose->first_busno, hose->last_busno);
 349         }
 350 #else
 351         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 352 #endif /* CONFIG_PCIE3 */
 353 }
 354
 355 #if defined(CONFIG_OF_BOARD_SETUP)
 356 void ft_board_pci_setup(void *blob, bd_t *bd)
 357 {
 358         /* TODO - make node name (eg pci0) dynamic */
 359 #ifdef CONFIG_PCI1
 360         ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 361 #endif
 362 #ifdef CONFIG_PCIE1
 363         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 364 #endif
 365 #ifdef CONFIG_PCIE2
 366         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 367 #endif
 368 #ifdef CONFIG_PCIE3
 369         ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
 370 #endif
 371 }
 372 #endif /* CONFIG_OF_BOARD_SETUP */