1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 NXP Semiconductors
4 * Author: Fabio Estevam <fabio.estevam@nxp.com>
7 #include <asm/arch/clock.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/mx7-pins.h>
10 #include <asm/arch/sys_proto.h>
12 #include <asm/mach-imx/hab.h>
13 #include <asm/mach-imx/iomux-v3.h>
14 #include <asm/mach-imx/mxc_i2c.h>
17 #include <fsl_esdhc.h>
20 #include <asm/arch/crm_regs.h>
23 #include <power/pmic.h>
24 #include <power/pfuze3000_pmic.h>
25 #include "../freescale/common/pfuze.h"
26 #include <asm/setup.h>
27 #include <asm/bootm.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
36 gd->ram_size = PHYS_SDRAM_SIZE;
38 /* Subtract the defined OPTEE runtime firmware length */
39 #ifdef CONFIG_OPTEE_TZDRAM_SIZE
40 gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
46 static iomux_v3_cfg_t const wdog_pads[] = {
47 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
50 static iomux_v3_cfg_t const uart1_pads[] = {
51 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
52 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
55 static void setup_iomux_uart(void)
57 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
60 int board_early_init_f(void)
68 int power_init_board(void)
71 int ret, dev_id, rev_id;
73 ret = pmic_get("pfuze3000", &dev);
79 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
80 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
81 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
83 /* disable Low Power Mode during standby mode */
84 pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
90 int board_eth_init(bd_t *bis)
94 #ifdef CONFIG_USB_ETHER
95 ret = usb_eth_initialize(bis);
97 printf("Error %d registering USB ether.\n", ret);
105 /* address of boot parameters */
106 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
115 if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
120 #ifdef CONFIG_OPTEE_TZDRAM_SIZE
121 unsigned long optee_start, optee_end;
123 optee_end = PHYS_SDRAM + PHYS_SDRAM_SIZE;
124 optee_start = optee_end - CONFIG_OPTEE_TZDRAM_SIZE;
126 printf("Board: WARP7 in %s mode OPTEE DRAM 0x%08lx-0x%08lx\n",
127 mode, optee_start, optee_end);
129 printf("Board: WARP7 in %s mode\n", mode);
135 int board_usb_phy_mode(int port)
137 return USB_INIT_DEVICE;
140 int board_late_init(void)
142 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
143 #ifdef CONFIG_SERIAL_TAG
144 struct tag_serialnr serialnr;
145 char serial_string[0x20];
148 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
150 set_wdog_reset(wdog);
153 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
154 * since we use PMIC_PWRON to reset the board.
156 clrsetbits_le16(&wdog->wcr, 0, 0x10);
158 #ifdef CONFIG_SECURE_BOOT
159 /* Determine HAB state */
160 env_set_ulong(HAB_ENABLED_ENVNAME, imx_hab_is_enabled());
162 env_set_ulong(HAB_ENABLED_ENVNAME, 0);
165 #ifdef CONFIG_SERIAL_TAG
166 /* Set serial# standard environment variable based on OTP settings */
167 get_board_serial(&serialnr);
168 snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
169 serialnr.low, serialnr.high);
170 env_set("serial#", serial_string);