1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2014 O.S. Systems Software LTDA.
6 * Author: Fabio Estevam <fabio.estevam@freescale.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mxc_hdmi.h>
15 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/video.h>
21 #include <asm/mach-imx/sata.h>
23 #include <linux/sizes.h>
29 #include <power/pmic.h>
30 #include <power/pfuze100_pmic.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
35 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
36 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
39 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
41 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
42 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
43 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
45 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
46 #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
47 #define REV_DETECTION IMX_GPIO_NR(2, 28)
49 static bool with_pmic;
53 gd->ram_size = imx_ddr_size();
58 static iomux_v3_cfg_t const uart1_pads[] = {
59 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
60 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
63 static iomux_v3_cfg_t const enet_pads[] = {
64 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
65 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
66 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
67 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
68 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
76 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
78 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 /* AR8031 PHY Reset */
80 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
83 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
85 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
88 static iomux_v3_cfg_t const rev_detection_pad[] = {
89 IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
92 static void setup_iomux_uart(void)
94 SETUP_IOMUX_PADS(uart1_pads);
97 static void setup_iomux_enet(void)
99 SETUP_IOMUX_PADS(enet_pads);
102 SETUP_IOMUX_PADS(enet_ar8035_power_pads);
103 /* enable AR8035 POWER */
104 gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
105 gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
107 /* wait until 3.3V of PHY and clock become stable */
110 /* Reset AR8031 PHY */
111 gpio_request(ETH_PHY_RESET, "PHY_RESET");
112 gpio_direction_output(ETH_PHY_RESET, 0);
114 gpio_set_value(ETH_PHY_RESET, 1);
118 static int ar8031_phy_fixup(struct phy_device *phydev)
123 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
124 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
125 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
126 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
128 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
130 mask = 0xffe7; /* AR8035 */
132 mask = 0xffe3; /* AR8031 */
136 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
138 /* introduce tx clock delay */
139 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
140 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
142 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
147 int board_phy_config(struct phy_device *phydev)
149 ar8031_phy_fixup(phydev);
151 if (phydev->drv->config)
152 phydev->drv->config(phydev);
157 #if defined(CONFIG_VIDEO_IPUV3)
158 struct i2c_pads_info mx6q_i2c2_pad_info = {
160 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
161 | MUX_PAD_CTRL(I2C_PAD_CTRL),
162 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
163 | MUX_PAD_CTRL(I2C_PAD_CTRL),
164 .gp = IMX_GPIO_NR(4, 12)
167 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
168 | MUX_PAD_CTRL(I2C_PAD_CTRL),
169 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
170 | MUX_PAD_CTRL(I2C_PAD_CTRL),
171 .gp = IMX_GPIO_NR(4, 13)
175 struct i2c_pads_info mx6dl_i2c2_pad_info = {
177 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
178 | MUX_PAD_CTRL(I2C_PAD_CTRL),
179 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
180 | MUX_PAD_CTRL(I2C_PAD_CTRL),
181 .gp = IMX_GPIO_NR(4, 12)
184 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
185 | MUX_PAD_CTRL(I2C_PAD_CTRL),
186 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
187 | MUX_PAD_CTRL(I2C_PAD_CTRL),
188 .gp = IMX_GPIO_NR(4, 13)
192 struct i2c_pads_info mx6q_i2c3_pad_info = {
194 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
195 | MUX_PAD_CTRL(I2C_PAD_CTRL),
196 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
197 | MUX_PAD_CTRL(I2C_PAD_CTRL),
198 .gp = IMX_GPIO_NR(1, 5)
201 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
202 | MUX_PAD_CTRL(I2C_PAD_CTRL),
203 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
204 | MUX_PAD_CTRL(I2C_PAD_CTRL),
205 .gp = IMX_GPIO_NR(7, 11)
209 struct i2c_pads_info mx6dl_i2c3_pad_info = {
211 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
212 | MUX_PAD_CTRL(I2C_PAD_CTRL),
213 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
214 | MUX_PAD_CTRL(I2C_PAD_CTRL),
215 .gp = IMX_GPIO_NR(1, 5)
218 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
219 | MUX_PAD_CTRL(I2C_PAD_CTRL),
220 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
221 | MUX_PAD_CTRL(I2C_PAD_CTRL),
222 .gp = IMX_GPIO_NR(7, 11)
226 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
227 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
228 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
229 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
230 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
231 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
232 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
233 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
234 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
235 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
236 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
237 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
238 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
239 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
240 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
241 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
242 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
243 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
244 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
245 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
246 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
247 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
248 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
249 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
250 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
251 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
254 static void do_enable_hdmi(struct display_info_t const *dev)
256 imx_enable_hdmi_phy();
259 static int detect_i2c(struct display_info_t const *dev)
262 struct udevice *bus, *udev;
265 rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
268 rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
273 return (0 == i2c_set_bus_num(dev->bus)) &&
274 (0 == i2c_probe(dev->addr));
278 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
280 SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
282 gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
283 gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
284 gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
285 gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
288 struct display_info_t const displays[] = {{
291 .pixfmt = IPU_PIX_FMT_RGB24,
292 .detect = detect_hdmi,
293 .enable = do_enable_hdmi,
307 .vmode = FB_VMODE_NONINTERLACED
311 .pixfmt = IPU_PIX_FMT_RGB666,
312 .detect = detect_i2c,
313 .enable = enable_fwadapt_7wvga,
315 .name = "FWBADAPT-LCD-F07A-0102",
327 .vmode = FB_VMODE_NONINTERLACED
329 size_t display_count = ARRAY_SIZE(displays);
331 static void setup_display(void)
333 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
339 reg = readl(&mxc_ccm->chsccdr);
340 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
341 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
342 writel(reg, &mxc_ccm->chsccdr);
344 /* Disable LCD backlight */
345 SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
346 gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
347 gpio_direction_input(IMX_GPIO_NR(4, 20));
349 #endif /* CONFIG_VIDEO_IPUV3 */
351 int board_eth_init(bd_t *bis)
355 return cpu_eth_init(bis);
358 int board_early_init_f(void)
368 #define PMIC_I2C_BUS 2
370 int power_init_board(void)
377 ret = pmic_get("pfuze100", &dev);
379 printf("pmic_get() ret %d\n", ret);
383 reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
385 printf("pmic_reg_read() ret %d\n", reg);
388 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
391 /* Set VGEN2 to 1.5V and enable */
392 reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
393 reg &= ~(LDO_VOL_MASK);
394 reg |= (LDOA_1_50V | (1 << (LDO_EN)));
395 pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
400 * Do not overwrite the console
401 * Use always serial for U-Boot console
403 int overwrite_console(void)
408 #ifdef CONFIG_CMD_BMODE
409 static const struct boot_mode board_boot_modes[] = {
410 /* 4 bit bus width */
411 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
412 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
417 static bool is_revc1(void)
419 SETUP_IOMUX_PADS(rev_detection_pad);
420 gpio_direction_input(REV_DETECTION);
422 if (gpio_get_value(REV_DETECTION))
428 static bool is_revd1(void)
436 int board_late_init(void)
438 #ifdef CONFIG_CMD_BMODE
439 add_board_boot_modes(board_boot_modes);
442 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
444 env_set("board_rev", "MX6QP");
446 env_set("board_rev", "MX6Q");
448 env_set("board_rev", "MX6DL");
451 env_set("board_name", "D1");
453 env_set("board_name", "C1");
455 env_set("board_name", "B1");
462 /* address of boot parameters */
463 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
465 #if defined(CONFIG_VIDEO_IPUV3)
466 setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
467 if (is_mx6dq() || is_mx6dqp()) {
468 setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6q_i2c2_pad_info);
469 setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6q_i2c3_pad_info);
471 setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
472 setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
483 gpio_request(REV_DETECTION, "REV_DETECT");
486 puts("Board: Wandboard rev D1\n");
488 puts("Board: Wandboard rev C1\n");
490 puts("Board: Wandboard rev B1\n");