board/wandboard/wandboard.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2014 O.S. Systems Software LTDA.
   5  *
   6  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/mxc_hdmi.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/video.h>
  21 #include <asm/mach-imx/sata.h>
  22 #include <asm/io.h>
  23 #include <linux/sizes.h>
  24 #include <common.h>
  25 #include <miiphy.h>
  26 #include <netdev.h>
  27 #include <phy.h>
  28 #include <i2c.h>
  29 #include <power/pmic.h>
  30 #include <power/pfuze100_pmic.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  35         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  36         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  39         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  40
  41 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  42         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  43         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  44
  45 #define ETH_PHY_RESET           IMX_GPIO_NR(3, 29)
  46 #define ETH_PHY_AR8035_POWER    IMX_GPIO_NR(7, 13)
  47 #define REV_DETECTION           IMX_GPIO_NR(2, 28)
  48
  49 /* Speed defined in Kconfig is only applicable when not using DM_I2C.  */
  50 #ifdef CONFIG_DM_I2C
  51 #define I2C1_SPEED_NON_DM       0
  52 #define I2C2_SPEED_NON_DM       0
  53 #else
  54 #define I2C1_SPEED_NON_DM       CONFIG_SYS_MXC_I2C1_SPEED
  55 #define I2C2_SPEED_NON_DM       CONFIG_SYS_MXC_I2C2_SPEED
  56 #endif
  57
  58 static bool with_pmic;
  59
  60 int dram_init(void)
  61 {
  62         gd->ram_size = imx_ddr_size();
  63
  64         return 0;
  65 }
  66
  67 static iomux_v3_cfg_t const uart1_pads[] = {
  68         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  69         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  70 };
  71
  72 static iomux_v3_cfg_t const enet_pads[] = {
  73         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  82         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  84         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  85         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  86         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  87         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  88         /* AR8031 PHY Reset */
  89         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90 };
  91
  92 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
  93         /* AR8035 POWER */
  94         IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95 };
  96
  97 static iomux_v3_cfg_t const rev_detection_pad[] = {
  98         IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  99 };
 100
 101 static void setup_iomux_uart(void)
 102 {
 103         SETUP_IOMUX_PADS(uart1_pads);
 104 }
 105
 106 static void setup_iomux_enet(void)
 107 {
 108         SETUP_IOMUX_PADS(enet_pads);
 109
 110         if (with_pmic) {
 111                 SETUP_IOMUX_PADS(enet_ar8035_power_pads);
 112                 /* enable AR8035 POWER */
 113                 gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
 114                 gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
 115         }
 116         /* wait until 3.3V of PHY and clock become stable */
 117         mdelay(10);
 118
 119         /* Reset AR8031 PHY */
 120         gpio_request(ETH_PHY_RESET, "PHY_RESET");
 121         gpio_direction_output(ETH_PHY_RESET, 0);
 122         mdelay(10);
 123         gpio_set_value(ETH_PHY_RESET, 1);
 124         udelay(100);
 125 }
 126
 127 static int ar8031_phy_fixup(struct phy_device *phydev)
 128 {
 129         unsigned short val;
 130         int mask;
 131
 132         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 133         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 134         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 135         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 136
 137         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 138         if (with_pmic)
 139                 mask = 0xffe7;  /* AR8035 */
 140         else
 141                 mask = 0xffe3;  /* AR8031 */
 142
 143         val &= mask;
 144         val |= 0x18;
 145         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 146
 147         /* introduce tx clock delay */
 148         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 149         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 150         val |= 0x0100;
 151         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 152
 153         return 0;
 154 }
 155
 156 int board_phy_config(struct phy_device *phydev)
 157 {
 158         ar8031_phy_fixup(phydev);
 159
 160         if (phydev->drv->config)
 161                 phydev->drv->config(phydev);
 162
 163         return 0;
 164 }
 165
 166 #if defined(CONFIG_VIDEO_IPUV3)
 167 struct i2c_pads_info mx6q_i2c2_pad_info = {
 168         .scl = {
 169                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
 170                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 171                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
 172                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 173                 .gp = IMX_GPIO_NR(4, 12)
 174         },
 175         .sda = {
 176                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
 177                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 178                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
 179                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 180                 .gp = IMX_GPIO_NR(4, 13)
 181         }
 182 };
 183
 184 struct i2c_pads_info mx6dl_i2c2_pad_info = {
 185         .scl = {
 186                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
 187                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 188                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
 189                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 190                 .gp = IMX_GPIO_NR(4, 12)
 191         },
 192         .sda = {
 193                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
 194                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 195                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
 196                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 197                 .gp = IMX_GPIO_NR(4, 13)
 198         }
 199 };
 200
 201 struct i2c_pads_info mx6q_i2c3_pad_info = {
 202         .scl = {
 203                 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
 204                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 205                 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
 206                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 207                 .gp = IMX_GPIO_NR(1, 5)
 208         },
 209         .sda = {
 210                 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
 211                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 212                 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
 213                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 214                 .gp = IMX_GPIO_NR(7, 11)
 215         }
 216 };
 217
 218 struct i2c_pads_info mx6dl_i2c3_pad_info = {
 219         .scl = {
 220                 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
 221                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 222                 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
 223                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 224                 .gp = IMX_GPIO_NR(1, 5)
 225         },
 226         .sda = {
 227                 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
 228                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 229                 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
 230                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 231                 .gp = IMX_GPIO_NR(7, 11)
 232         }
 233 };
 234
 235 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
 236         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
 237         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
 238         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
 239         IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
 240         IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
 241         IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
 242         IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
 243         IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
 244         IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
 245         IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
 246         IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
 247         IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
 248         IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
 249         IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
 250         IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
 251         IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
 252         IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
 253         IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
 254         IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
 255         IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
 256         IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
 257         IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
 258         IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
 259         IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
 260         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
 261 };
 262
 263 static void do_enable_hdmi(struct display_info_t const *dev)
 264 {
 265         imx_enable_hdmi_phy();
 266 }
 267
 268 static int detect_i2c(struct display_info_t const *dev)
 269 {
 270 #ifdef CONFIG_DM_I2C
 271         struct udevice *bus, *udev;
 272         int rc;
 273
 274         rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
 275         if (rc)
 276                 return rc;
 277         rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
 278         if (rc)
 279                 return 0;
 280         return 1;
 281 #else
 282         return (0 == i2c_set_bus_num(dev->bus)) &&
 283                         (0 == i2c_probe(dev->addr));
 284 #endif
 285 }
 286
 287 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
 288 {
 289         SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
 290
 291         gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
 292         gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
 293         gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
 294         gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
 295 }
 296
 297 struct display_info_t const displays[] = {{
 298         .bus    = -1,
 299         .addr   = 0,
 300         .pixfmt = IPU_PIX_FMT_RGB24,
 301         .detect = detect_hdmi,
 302         .enable = do_enable_hdmi,
 303         .mode   = {
 304                 .name           = "HDMI",
 305                 .refresh        = 60,
 306                 .xres           = 1024,
 307                 .yres           = 768,
 308                 .pixclock       = 15385,
 309                 .left_margin    = 220,
 310                 .right_margin   = 40,
 311                 .upper_margin   = 21,
 312                 .lower_margin   = 7,
 313                 .hsync_len      = 60,
 314                 .vsync_len      = 10,
 315                 .sync           = FB_SYNC_EXT,
 316                 .vmode          = FB_VMODE_NONINTERLACED
 317 } }, {
 318         .bus    = 1,
 319         .addr   = 0x10,
 320         .pixfmt = IPU_PIX_FMT_RGB666,
 321         .detect = detect_i2c,
 322         .enable = enable_fwadapt_7wvga,
 323         .mode   = {
 324                 .name           = "FWBADAPT-LCD-F07A-0102",
 325                 .refresh        = 60,
 326                 .xres           = 800,
 327                 .yres           = 480,
 328                 .pixclock       = 33260,
 329                 .left_margin    = 128,
 330                 .right_margin   = 128,
 331                 .upper_margin   = 22,
 332                 .lower_margin   = 22,
 333                 .hsync_len      = 1,
 334                 .vsync_len      = 1,
 335                 .sync           = 0,
 336                 .vmode          = FB_VMODE_NONINTERLACED
 337 } } };
 338 size_t display_count = ARRAY_SIZE(displays);
 339
 340 static void setup_display(void)
 341 {
 342         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 343         int reg;
 344
 345         enable_ipu_clock();
 346         imx_setup_hdmi();
 347
 348         reg = readl(&mxc_ccm->chsccdr);
 349         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 350                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 351         writel(reg, &mxc_ccm->chsccdr);
 352
 353         /* Disable LCD backlight */
 354         SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
 355         gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
 356         gpio_direction_input(IMX_GPIO_NR(4, 20));
 357 }
 358 #endif /* CONFIG_VIDEO_IPUV3 */
 359
 360 int board_eth_init(bd_t *bis)
 361 {
 362         setup_iomux_enet();
 363
 364         return cpu_eth_init(bis);
 365 }
 366
 367 int board_early_init_f(void)
 368 {
 369         setup_iomux_uart();
 370 #ifdef CONFIG_SATA
 371         setup_sata();
 372 #endif
 373
 374         return 0;
 375 }
 376
 377 #define PMIC_I2C_BUS            2
 378
 379 int power_init_board(void)
 380 {
 381         struct udevice *dev;
 382         int reg, ret;
 383
 384         puts("PMIC:  ");
 385
 386         ret = pmic_get("pfuze100", &dev);
 387         if (ret < 0) {
 388                 printf("pmic_get() ret %d\n", ret);
 389                 return 0;
 390         }
 391
 392         reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
 393         if (reg < 0) {
 394                 printf("pmic_reg_read() ret %d\n", reg);
 395                 return 0;
 396         }
 397         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 398         with_pmic = true;
 399
 400         /* Set VGEN2 to 1.5V and enable */
 401         reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
 402         reg &= ~(LDO_VOL_MASK);
 403         reg |= (LDOA_1_50V | (1 << (LDO_EN)));
 404         pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
 405         return 0;
 406 }
 407
 408 /*
 409  * Do not overwrite the console
 410  * Use always serial for U-Boot console
 411  */
 412 int overwrite_console(void)
 413 {
 414         return 1;
 415 }
 416
 417 #ifdef CONFIG_CMD_BMODE
 418 static const struct boot_mode board_boot_modes[] = {
 419         /* 4 bit bus width */
 420         {"mmc0",          MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 421         {"mmc1",          MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 422         {NULL,   0},
 423 };
 424 #endif
 425
 426 static bool is_revc1(void)
 427 {
 428         SETUP_IOMUX_PADS(rev_detection_pad);
 429         gpio_direction_input(REV_DETECTION);
 430
 431         if (gpio_get_value(REV_DETECTION))
 432                 return true;
 433         else
 434                 return false;
 435 }
 436
 437 static bool is_revd1(void)
 438 {
 439         if (with_pmic)
 440                 return true;
 441         else
 442                 return false;
 443 }
 444
 445 int board_late_init(void)
 446 {
 447 #ifdef CONFIG_CMD_BMODE
 448         add_board_boot_modes(board_boot_modes);
 449 #endif
 450
 451 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 452         if (is_mx6dqp())
 453                 env_set("board_rev", "MX6QP");
 454         else if (is_mx6dq())
 455                 env_set("board_rev", "MX6Q");
 456         else
 457                 env_set("board_rev", "MX6DL");
 458
 459         if (is_revd1())
 460                 env_set("board_name", "D1");
 461         else if (is_revc1())
 462                 env_set("board_name", "C1");
 463         else
 464                 env_set("board_name", "B1");
 465 #endif
 466         return 0;
 467 }
 468
 469 int board_init(void)
 470 {
 471         /* address of boot parameters */
 472         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 473
 474 #if defined(CONFIG_VIDEO_IPUV3)
 475         setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
 476         if (is_mx6dq() || is_mx6dqp()) {
 477                 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
 478                 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
 479         } else {
 480                 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
 481                 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
 482         }
 483
 484         setup_display();
 485 #endif
 486
 487         return 0;
 488 }
 489
 490 int checkboard(void)
 491 {
 492         gpio_request(REV_DETECTION, "REV_DETECT");
 493
 494         if (is_revd1())
 495                 puts("Board: Wandboard rev D1\n");
 496         else if (is_revc1())
 497                 puts("Board: Wandboard rev C1\n");
 498         else
 499                 puts("Board: Wandboard rev B1\n");
 500
 501         return 0;
 502 }
 503
 504 #ifdef CONFIG_SPL_LOAD_FIT
 505 int board_fit_config_name_match(const char *name)
 506 {
 507         if (is_mx6dq()) {
 508                 if (!strcmp(name, "imx6q-wandboard-revb1"))
 509                         return 0;
 510         } else if (is_mx6dqp()) {
 511                 if (!strcmp(name, "imx6qp-wandboard-revd1"))
 512                         return 0;
 513         } else if (is_mx6dl() || is_mx6solo()) {
 514                 if (!strcmp(name, "imx6dl-wandboard-revb1"))
 515                         return 0;
 516         }
 517
 518         return -EINVAL;
 519 }
 520 #endif