1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2014 O.S. Systems Software LTDA.
6 * Author: Fabio Estevam <fabio.estevam@freescale.com>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/mxc_hdmi.h>
16 #include <asm/arch/sys_proto.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/mxc_i2c.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <asm/mach-imx/video.h>
22 #include <asm/mach-imx/sata.h>
25 #include <linux/sizes.h>
31 #include <power/pmic.h>
32 #include <power/pfuze100_pmic.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
37 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
41 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
43 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
45 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
47 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
48 #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
49 #define REV_DETECTION IMX_GPIO_NR(2, 28)
51 /* Speed defined in Kconfig is only applicable when not using DM_I2C. */
53 #define I2C1_SPEED_NON_DM 0
54 #define I2C2_SPEED_NON_DM 0
56 #define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED
57 #define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED
60 static bool with_pmic;
64 gd->ram_size = imx_ddr_size();
69 static iomux_v3_cfg_t const uart1_pads[] = {
70 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
71 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
74 static iomux_v3_cfg_t const enet_pads[] = {
75 /* AR8031 PHY Reset */
76 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
79 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
81 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
84 static iomux_v3_cfg_t const rev_detection_pad[] = {
85 IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
88 static void setup_iomux_uart(void)
90 SETUP_IOMUX_PADS(uart1_pads);
93 static void setup_iomux_enet(void)
95 SETUP_IOMUX_PADS(enet_pads);
98 SETUP_IOMUX_PADS(enet_ar8035_power_pads);
99 /* enable AR8035 POWER */
100 gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
101 gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
103 /* wait until 3.3V of PHY and clock become stable */
106 /* Reset AR8031 PHY */
107 gpio_request(ETH_PHY_RESET, "PHY_RESET");
108 gpio_direction_output(ETH_PHY_RESET, 0);
110 gpio_set_value(ETH_PHY_RESET, 1);
114 static int ar8031_phy_fixup(struct phy_device *phydev)
119 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
120 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
121 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
122 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
124 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
126 mask = 0xffe7; /* AR8035 */
128 mask = 0xffe3; /* AR8031 */
132 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
134 /* introduce tx clock delay */
135 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
136 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
138 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
143 int board_phy_config(struct phy_device *phydev)
145 ar8031_phy_fixup(phydev);
147 if (phydev->drv->config)
148 phydev->drv->config(phydev);
153 #if defined(CONFIG_VIDEO_IPUV3)
154 struct i2c_pads_info mx6q_i2c2_pad_info = {
156 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
157 | MUX_PAD_CTRL(I2C_PAD_CTRL),
158 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
159 | MUX_PAD_CTRL(I2C_PAD_CTRL),
160 .gp = IMX_GPIO_NR(4, 12)
163 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
164 | MUX_PAD_CTRL(I2C_PAD_CTRL),
165 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
166 | MUX_PAD_CTRL(I2C_PAD_CTRL),
167 .gp = IMX_GPIO_NR(4, 13)
171 struct i2c_pads_info mx6dl_i2c2_pad_info = {
173 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
174 | MUX_PAD_CTRL(I2C_PAD_CTRL),
175 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
176 | MUX_PAD_CTRL(I2C_PAD_CTRL),
177 .gp = IMX_GPIO_NR(4, 12)
180 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
181 | MUX_PAD_CTRL(I2C_PAD_CTRL),
182 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
183 | MUX_PAD_CTRL(I2C_PAD_CTRL),
184 .gp = IMX_GPIO_NR(4, 13)
188 struct i2c_pads_info mx6q_i2c3_pad_info = {
190 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
191 | MUX_PAD_CTRL(I2C_PAD_CTRL),
192 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
193 | MUX_PAD_CTRL(I2C_PAD_CTRL),
194 .gp = IMX_GPIO_NR(1, 5)
197 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
198 | MUX_PAD_CTRL(I2C_PAD_CTRL),
199 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
200 | MUX_PAD_CTRL(I2C_PAD_CTRL),
201 .gp = IMX_GPIO_NR(7, 11)
205 struct i2c_pads_info mx6dl_i2c3_pad_info = {
207 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
208 | MUX_PAD_CTRL(I2C_PAD_CTRL),
209 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
210 | MUX_PAD_CTRL(I2C_PAD_CTRL),
211 .gp = IMX_GPIO_NR(1, 5)
214 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
215 | MUX_PAD_CTRL(I2C_PAD_CTRL),
216 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
217 | MUX_PAD_CTRL(I2C_PAD_CTRL),
218 .gp = IMX_GPIO_NR(7, 11)
222 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
223 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
224 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
225 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
226 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
227 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
228 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
229 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
230 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
231 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
232 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
233 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
234 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
235 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
236 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
237 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
238 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
239 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
240 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
241 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
242 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
243 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
244 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
245 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
246 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
247 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
250 static void do_enable_hdmi(struct display_info_t const *dev)
252 imx_enable_hdmi_phy();
255 static int detect_i2c(struct display_info_t const *dev)
258 struct udevice *bus, *udev;
261 rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
264 rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
269 return (0 == i2c_set_bus_num(dev->bus)) &&
270 (0 == i2c_probe(dev->addr));
274 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
276 SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
278 gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
279 gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
280 gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
281 gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
284 struct display_info_t const displays[] = {{
287 .pixfmt = IPU_PIX_FMT_RGB24,
288 .detect = detect_hdmi,
289 .enable = do_enable_hdmi,
303 .vmode = FB_VMODE_NONINTERLACED
307 .pixfmt = IPU_PIX_FMT_RGB666,
308 .detect = detect_i2c,
309 .enable = enable_fwadapt_7wvga,
311 .name = "FWBADAPT-LCD-F07A-0102",
323 .vmode = FB_VMODE_NONINTERLACED
325 size_t display_count = ARRAY_SIZE(displays);
327 static void setup_display(void)
329 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
335 reg = readl(&mxc_ccm->chsccdr);
336 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
337 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
338 writel(reg, &mxc_ccm->chsccdr);
340 /* Disable LCD backlight */
341 SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
342 gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
343 gpio_direction_input(IMX_GPIO_NR(4, 20));
345 #endif /* CONFIG_VIDEO_IPUV3 */
347 int board_early_init_f(void)
357 #define PMIC_I2C_BUS 2
359 int power_init_board(void)
364 ret = pmic_get("pfuze100@8", &dev);
366 debug("pmic_get() ret %d\n", ret);
370 reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
372 printf("pmic_reg_read() ret %d\n", reg);
375 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
378 /* Set VGEN2 to 1.5V and enable */
379 reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
380 reg &= ~(LDO_VOL_MASK);
381 reg |= (LDOA_1_50V | (1 << (LDO_EN)));
382 pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
387 * Do not overwrite the console
388 * Use always serial for U-Boot console
390 int overwrite_console(void)
395 #ifdef CONFIG_CMD_BMODE
396 static const struct boot_mode board_boot_modes[] = {
397 /* 4 bit bus width */
398 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
399 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
404 static bool is_revc1(void)
406 SETUP_IOMUX_PADS(rev_detection_pad);
407 gpio_direction_input(REV_DETECTION);
409 if (gpio_get_value(REV_DETECTION))
415 static bool is_revd1(void)
423 int board_late_init(void)
425 #ifdef CONFIG_CMD_BMODE
426 add_board_boot_modes(board_boot_modes);
429 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
431 env_set("board_rev", "MX6QP");
433 env_set("board_rev", "MX6Q");
435 env_set("board_rev", "MX6DL");
438 env_set("board_name", "D1");
440 env_set("board_name", "C1");
442 env_set("board_name", "B1");
450 /* address of boot parameters */
451 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
453 #if defined(CONFIG_VIDEO_IPUV3)
454 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
455 if (is_mx6dq() || is_mx6dqp()) {
456 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
457 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
459 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
460 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
471 gpio_request(REV_DETECTION, "REV_DETECT");
474 puts("Board: Wandboard rev D1\n");
476 puts("Board: Wandboard rev C1\n");
478 puts("Board: Wandboard rev B1\n");
483 #ifdef CONFIG_SPL_LOAD_FIT
484 int board_fit_config_name_match(const char *name)
487 if (!strcmp(name, "imx6q-wandboard-revb1"))
489 } else if (is_mx6dqp()) {
490 if (!strcmp(name, "imx6qp-wandboard-revd1"))
492 } else if (is_mx6dl() || is_mx6solo()) {
493 if (!strcmp(name, "imx6dl-wandboard-revb1"))