1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2014 O.S. Systems Software LTDA.
6 * Author: Fabio Estevam <fabio.estevam@freescale.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mxc_hdmi.h>
15 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/video.h>
21 #include <asm/mach-imx/sata.h>
23 #include <linux/sizes.h>
25 #include <fsl_esdhc.h>
31 #include <power/pmic.h>
32 #include <power/pfuze100_pmic.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
37 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
41 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
45 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
49 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
51 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
52 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
53 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
54 #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
55 #define REV_DETECTION IMX_GPIO_NR(2, 28)
57 static bool with_pmic;
61 gd->ram_size = imx_ddr_size();
66 static iomux_v3_cfg_t const uart1_pads[] = {
67 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
68 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
71 static iomux_v3_cfg_t const usdhc1_pads[] = {
72 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
73 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
74 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
75 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
76 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
78 /* Carrier MicroSD Card Detect */
79 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
82 static iomux_v3_cfg_t const usdhc3_pads[] = {
83 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
84 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
85 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
86 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
87 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
88 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
89 /* SOM MicroSD Card Detect */
90 IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 static iomux_v3_cfg_t const enet_pads[] = {
94 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
95 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
96 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
97 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
98 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
99 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
100 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
101 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
102 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
103 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
104 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
105 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
106 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
107 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
108 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
109 /* AR8031 PHY Reset */
110 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
113 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
115 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
118 static iomux_v3_cfg_t const rev_detection_pad[] = {
119 IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
122 static void setup_iomux_uart(void)
124 SETUP_IOMUX_PADS(uart1_pads);
127 static void setup_iomux_enet(void)
129 SETUP_IOMUX_PADS(enet_pads);
132 SETUP_IOMUX_PADS(enet_ar8035_power_pads);
133 /* enable AR8035 POWER */
134 gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
135 gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
137 /* wait until 3.3V of PHY and clock become stable */
140 /* Reset AR8031 PHY */
141 gpio_request(ETH_PHY_RESET, "PHY_RESET");
142 gpio_direction_output(ETH_PHY_RESET, 0);
144 gpio_set_value(ETH_PHY_RESET, 1);
148 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
153 int board_mmc_getcd(struct mmc *mmc)
155 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
158 switch (cfg->esdhc_base) {
159 case USDHC1_BASE_ADDR:
160 ret = !gpio_get_value(USDHC1_CD_GPIO);
162 case USDHC3_BASE_ADDR:
163 ret = !gpio_get_value(USDHC3_CD_GPIO);
170 int board_mmc_init(bd_t *bis)
175 #if !CONFIG_IS_ENABLED(DM_MMC)
176 gpio_request(USDHC1_CD_GPIO, "USDHC1_CD");
177 gpio_request(USDHC3_CD_GPIO, "USDHC3_CD");
181 * Following map is done:
182 * (U-Boot device node) (Physical Port)
184 * mmc1 Carrier board MicroSD
186 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
189 SETUP_IOMUX_PADS(usdhc3_pads);
190 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
191 usdhc_cfg[0].max_bus_width = 4;
192 gpio_direction_input(USDHC3_CD_GPIO);
195 SETUP_IOMUX_PADS(usdhc1_pads);
196 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
197 usdhc_cfg[1].max_bus_width = 4;
198 gpio_direction_input(USDHC1_CD_GPIO);
201 printf("Warning: you configured more USDHC controllers"
202 "(%d) then supported by the board (%d)\n",
203 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
207 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
215 static int ar8031_phy_fixup(struct phy_device *phydev)
220 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
221 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
222 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
223 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
225 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
227 mask = 0xffe7; /* AR8035 */
229 mask = 0xffe3; /* AR8031 */
233 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
235 /* introduce tx clock delay */
236 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
237 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
239 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
244 int board_phy_config(struct phy_device *phydev)
246 ar8031_phy_fixup(phydev);
248 if (phydev->drv->config)
249 phydev->drv->config(phydev);
254 #if defined(CONFIG_VIDEO_IPUV3)
255 struct i2c_pads_info mx6q_i2c2_pad_info = {
257 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
258 | MUX_PAD_CTRL(I2C_PAD_CTRL),
259 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
260 | MUX_PAD_CTRL(I2C_PAD_CTRL),
261 .gp = IMX_GPIO_NR(4, 12)
264 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
265 | MUX_PAD_CTRL(I2C_PAD_CTRL),
266 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
267 | MUX_PAD_CTRL(I2C_PAD_CTRL),
268 .gp = IMX_GPIO_NR(4, 13)
272 struct i2c_pads_info mx6dl_i2c2_pad_info = {
274 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
275 | MUX_PAD_CTRL(I2C_PAD_CTRL),
276 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
277 | MUX_PAD_CTRL(I2C_PAD_CTRL),
278 .gp = IMX_GPIO_NR(4, 12)
281 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
282 | MUX_PAD_CTRL(I2C_PAD_CTRL),
283 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
284 | MUX_PAD_CTRL(I2C_PAD_CTRL),
285 .gp = IMX_GPIO_NR(4, 13)
289 struct i2c_pads_info mx6q_i2c3_pad_info = {
291 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
292 | MUX_PAD_CTRL(I2C_PAD_CTRL),
293 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
294 | MUX_PAD_CTRL(I2C_PAD_CTRL),
295 .gp = IMX_GPIO_NR(1, 5)
298 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
299 | MUX_PAD_CTRL(I2C_PAD_CTRL),
300 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
301 | MUX_PAD_CTRL(I2C_PAD_CTRL),
302 .gp = IMX_GPIO_NR(7, 11)
306 struct i2c_pads_info mx6dl_i2c3_pad_info = {
308 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
309 | MUX_PAD_CTRL(I2C_PAD_CTRL),
310 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
311 | MUX_PAD_CTRL(I2C_PAD_CTRL),
312 .gp = IMX_GPIO_NR(1, 5)
315 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
316 | MUX_PAD_CTRL(I2C_PAD_CTRL),
317 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
318 | MUX_PAD_CTRL(I2C_PAD_CTRL),
319 .gp = IMX_GPIO_NR(7, 11)
323 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
324 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
325 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
326 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
327 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
328 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
329 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
330 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
331 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
332 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
333 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
334 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
335 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
336 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
337 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
338 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
339 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
340 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
341 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
342 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
343 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
344 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
345 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
346 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
347 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
348 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
351 static void do_enable_hdmi(struct display_info_t const *dev)
353 imx_enable_hdmi_phy();
356 static int detect_i2c(struct display_info_t const *dev)
358 return (0 == i2c_set_bus_num(dev->bus)) &&
359 (0 == i2c_probe(dev->addr));
362 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
364 SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
366 gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
367 gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
368 gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
369 gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
372 struct display_info_t const displays[] = {{
375 .pixfmt = IPU_PIX_FMT_RGB24,
376 .detect = detect_hdmi,
377 .enable = do_enable_hdmi,
391 .vmode = FB_VMODE_NONINTERLACED
395 .pixfmt = IPU_PIX_FMT_RGB666,
396 .detect = detect_i2c,
397 .enable = enable_fwadapt_7wvga,
399 .name = "FWBADAPT-LCD-F07A-0102",
411 .vmode = FB_VMODE_NONINTERLACED
413 size_t display_count = ARRAY_SIZE(displays);
415 static void setup_display(void)
417 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
423 reg = readl(&mxc_ccm->chsccdr);
424 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
425 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
426 writel(reg, &mxc_ccm->chsccdr);
428 /* Disable LCD backlight */
429 SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
430 gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
431 gpio_direction_input(IMX_GPIO_NR(4, 20));
433 #endif /* CONFIG_VIDEO_IPUV3 */
435 int board_eth_init(bd_t *bis)
439 return cpu_eth_init(bis);
442 int board_early_init_f(void)
452 #define PMIC_I2C_BUS 2
454 int power_init_board(void)
461 ret = pmic_get("pfuze100", &dev);
463 printf("pmic_get() ret %d\n", ret);
467 reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
469 printf("pmic_reg_read() ret %d\n", reg);
472 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
475 /* Set VGEN2 to 1.5V and enable */
476 reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
477 reg &= ~(LDO_VOL_MASK);
478 reg |= (LDOA_1_50V | (1 << (LDO_EN)));
479 pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
484 * Do not overwrite the console
485 * Use always serial for U-Boot console
487 int overwrite_console(void)
492 #ifdef CONFIG_CMD_BMODE
493 static const struct boot_mode board_boot_modes[] = {
494 /* 4 bit bus width */
495 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
496 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
501 static bool is_revc1(void)
503 SETUP_IOMUX_PADS(rev_detection_pad);
504 gpio_direction_input(REV_DETECTION);
506 if (gpio_get_value(REV_DETECTION))
512 static bool is_revd1(void)
520 int board_late_init(void)
522 #ifdef CONFIG_CMD_BMODE
523 add_board_boot_modes(board_boot_modes);
526 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
528 env_set("board_rev", "MX6QP");
530 env_set("board_rev", "MX6Q");
532 env_set("board_rev", "MX6DL");
535 env_set("board_name", "D1");
537 env_set("board_name", "C1");
539 env_set("board_name", "B1");
546 /* address of boot parameters */
547 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
549 #if defined(CONFIG_VIDEO_IPUV3)
550 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
551 if (is_mx6dq() || is_mx6dqp()) {
552 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
553 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
555 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
556 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
567 gpio_request(REV_DETECTION, "REV_DETECT");
570 puts("Board: Wandboard rev D1\n");
572 puts("Board: Wandboard rev C1\n");
574 puts("Board: Wandboard rev B1\n");