3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
5 * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/processor.h>
13 #include <linux/compiler.h>
17 fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr)
20 volatile unsigned long val;
21 volatile unsigned short *dest = daddr; /* volatile-bypass optimizer */
23 for (i = 0; i < len; i++, src++) {
25 *dest = (unsigned short) ((val & 0xff000000L) >> 16);
26 *dest = (unsigned short) ((val & 0x00ff0000L) >> 8);
27 *dest = (unsigned short) (val & 0x0000ff00L);
28 *dest = (unsigned short) ((val & 0x000000ffL) << 8);
31 /* Terminate programming with 4 C clocks */
33 val = *(unsigned short *) dest;
34 val = *(unsigned short *) dest;
35 val = *(unsigned short *) dest;
36 val = *(unsigned short *) dest;
42 fpgaDownload(unsigned char *saddr, unsigned long size, unsigned short *daddr)
44 int i; /* index, intr disable flag */
45 int start; /* timer */
46 unsigned long greg, grego; /* GPIO & output register */
47 unsigned long length; /* image size in words */
48 unsigned long *source; /* image source addr */
49 unsigned short *dest; /* destination FPGA addr */
50 volatile unsigned short *ndest; /* temp dest FPGA addr */
51 unsigned long cnfg = GPIO_XCV_CNFG; /* FPGA CNFG */
52 unsigned long eirq = GPIO_XCV_IRQ;
53 int retval = -1; /* Function return value */
54 __maybe_unused volatile unsigned short val; /* temp val */
56 /* Setup some basic values */
57 length = (size / 4) + 1; /* size in words, rounding UP
59 source = (unsigned long *) saddr;
60 dest = (unsigned short *) daddr;
62 /* Get DCR output register */
63 grego = in32(PPC405GP_GPIO0_OR);
66 grego &= ~GPIO_XCV_PROG; /* PROG line low */
67 out32(PPC405GP_GPIO0_OR, grego);
69 /* Setup timeout timer */
72 /* Wait for FPGA init line to go low */
73 while (in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) {
74 /* Check for timeout - 100us max, so use 3ms */
75 if (get_timer(start) > 3) {
76 printf(" failed to start init.\n");
77 log_warn(ERR_XINIT0); /* Don't halt */
79 /* Reset line stays low */
80 goto done; /* I like gotos... */
85 grego |= GPIO_XCV_PROG; /* PROG line high */
86 out32(PPC405GP_GPIO0_OR, grego);
88 /* Wait for FPGA end of init period = init line go hi */
89 while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) {
91 /* Check for timeout */
92 if (get_timer(start) > 3) {
93 printf(" failed to exit init.\n");
97 grego &= ~GPIO_XCV_PROG; /* PROG line low */
98 out32(PPC405GP_GPIO0_OR, grego);
104 /* Now program FPGA ... */
106 for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
107 /* Toggle IRQ/GPIO */
108 greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
109 greg |= eirq; /* toggle irq/gpio */
110 mtdcr(CPC0_CR0, greg); /* ... just do it */
112 /* turn on open drain for CNFG */
113 greg = in32(PPC405GP_GPIO0_ODR); /* get open drain register */
114 greg |= cnfg; /* CNFG open drain */
115 out32(PPC405GP_GPIO0_ODR, greg); /* .. just do it */
117 /* Turn output enable on for CNFG */
118 greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
119 greg |= cnfg; /* CNFG tristate inactive */
120 out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
122 /* Setup FPGA for programming */
123 grego &= ~cnfg; /* CONFIG line low */
124 out32(PPC405GP_GPIO0_OR, grego);
129 printf("\n destination: 0x%lx ", (unsigned long) ndest);
131 fpga_img_write(source, length, (unsigned short *) ndest);
133 /* Done programming */
134 grego |= cnfg; /* CONFIG line high */
135 out32(PPC405GP_GPIO0_OR, grego);
137 /* Turn output enable OFF for CNFG */
138 greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
139 greg &= ~cnfg; /* CNFG tristate inactive */
140 out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
142 /* Toggle IRQ/GPIO */
143 greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
144 greg &= ~eirq; /* toggle irq/gpio */
145 mtdcr(CPC0_CR0, greg); /* ... just do it */
147 /* XXX - Next FPGA addr */
148 ndest = (unsigned short *) ((char *) ndest + 0x00100000L);
149 cnfg >>= 1; /* XXX - Next */
153 /* Terminate programming with 4 C clocks */
155 for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
160 ndest = (unsigned short *) ((char *) ndest + 0x00100000L);
164 start = get_timer(0);
166 /* Wait for FPGA end of programming period = Test DONE low */
167 while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) {
169 /* Check for timeout */
170 if (get_timer(start) > 3) {
171 printf(" done failed to come high.\n");
172 log_warn(ERR_XDONE1);
175 grego &= ~GPIO_XCV_PROG; /* PROG line low */
176 out32(PPC405GP_GPIO0_OR, grego);
182 printf("\n FPGA load succeeded\n");
183 retval = 0; /* Program OK */
189 /* FPGA image is stored in flash */
190 extern flash_info_t flash_info[];
194 unsigned int i, j, ptr; /* General purpose */
195 unsigned char bufchar; /* General purpose character */
196 unsigned char *buf; /* Start of image pointer */
197 unsigned long len; /* Length of image */
198 unsigned char *fn_buf; /* Start of filename string */
199 unsigned int fn_len; /* Length of filename string */
200 unsigned char *xcv_buf; /* Pointer to start of image */
201 unsigned long xcv_len; /* Length of image */
202 unsigned long crc; /* 30bit crc in image */
203 unsigned long calc_crc; /* Calc'd 30bit crc */
206 /* Tell the world what we are doing */
210 * Get address of first sector where the FPGA
213 buf = (unsigned char *) flash_info[1].start[0];
216 * Get the stored image's CRC & length.
218 crc = *(unsigned long *) (buf + 4); /* CRC is first long word */
219 len = *(unsigned long *) (buf + 8); /* Image len is next long */
222 if ((len < 0x133A4) || (len > 0x80000))
226 * Get the file name pointer and length.
227 * filename length is next short
229 fn_len = (*(unsigned short *) (buf + 12) & 0xff);
233 * Get the FPGA image pointer and length length.
235 xcv_buf = fn_buf + fn_len; /* pointer to fpga image */
236 xcv_len = len - 14 - fn_len; /* fpga image length */
238 /* Check for uninitialized FLASH */
239 if ((strncmp((char *) buf, "w7o", 3) != 0) || (len > 0x0007ffffL)
244 * Calculate and Check the image's CRC.
246 calc_crc = crc32(0, xcv_buf, xcv_len);
247 if (crc != calc_crc) {
248 printf("\nfailed - bad CRC\n");
252 /* Output the file name */
253 printf("file name : ");
254 for (i = 0; i < fn_len; i++) {
255 bufchar = fn_buf[+i];
256 if (bufchar < ' ' || bufchar > '~')
262 * find rest of display data
264 ptr = 15; /* Offset to ncd filename
265 length in fpga image */
266 j = xcv_buf[ptr]; /* Get len of ncd filename */
269 ptr = ptr + j + 3; /* skip ncd filename string +
270 3 bytes more bytes */
273 * output target device string
275 j = xcv_buf[ptr++] - 1; /* len of targ str less term */
278 printf("\n target : ");
279 for (i = 0; i < j; i++) {
280 bufchar = (xcv_buf[ptr++]);
281 if (bufchar < ' ' || bufchar > '~')
287 * output compilation date string and time string
289 ptr += 3; /* skip 2 bytes */
290 printf("\n synth time : ");
291 j = (xcv_buf[ptr++] - 1); /* len of date str less term */
294 for (i = 0; i < j; i++) {
295 bufchar = (xcv_buf[ptr++]);
296 if (bufchar < ' ' || bufchar > '~')
301 ptr += 3; /* Skip 2 bytes */
303 j = (xcv_buf[ptr++] - 1); /* slen = targ dev str len */
306 for (i = 0; i < j; i++) {
307 bufchar = (xcv_buf[ptr++]);
308 if (bufchar < ' ' || bufchar > '~')
314 * output crc and length strings
316 printf("\n len & crc : 0x%lx 0x%lx", len, crc);
321 retval = fpgaDownload((unsigned char *) xcv_buf, xcv_len,
322 (unsigned short *) 0xfd000000L);
326 printf("\n BAD FPGA image format @ %lx\n",
327 flash_info[1].start[0]);
328 log_warn(ERR_XIMAGE);
333 void test_fpga(unsigned short *daddr)
336 volatile unsigned short *ndest = daddr;
338 for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
339 #if defined(CONFIG_W7OLMG)
340 ndest[0x7e] = 0x55aa;
341 if (ndest[0x7e] != 0x55aa)
342 log_warn(ERR_XRW1 + i);
343 ndest[0x7e] = 0xaa55;
344 if (ndest[0x7e] != 0xaa55)
345 log_warn(ERR_XRW1 + i);
346 ndest[0x7e] = 0xc318;
347 if (ndest[0x7e] != 0xc318)
348 log_warn(ERR_XRW1 + i);
350 #elif defined(CONFIG_W7OLMC)
351 ndest[0x800] = 0x55aa;
352 ndest[0x801] = 0xaa55;
353 ndest[0x802] = 0xc318;
354 ndest[0x4800] = 0x55aa;
355 ndest[0x4801] = 0xaa55;
356 ndest[0x4802] = 0xc318;
357 if ((ndest[0x800] != 0x55aa) ||
358 (ndest[0x801] != 0xaa55) || (ndest[0x802] != 0xc318))
359 log_warn(ERR_XRW1 + (2 * i)); /* Auto gen error code */
360 if ((ndest[0x4800] != 0x55aa) ||
361 (ndest[0x4801] != 0xaa55) || (ndest[0x4802] != 0xc318))
362 log_warn(ERR_XRW2 + (2 * i)); /* Auto gen error code */
365 #error "Unknown W7O board configuration"
369 printf(" FPGA ready\n");