1 // SPDX-License-Identifier: GPL-2.0+
5 * Board functions for TI AM335X based boards
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
12 #include <linux/libfdt.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
23 #include <asm/arch/mux.h>
30 #include <power/tps65217.h>
31 #include <power/tps65910.h>
32 #include <environment.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 /* GPIO that controls power to DDR on EVM-SK */
39 #define GPIO_DDR_VTT_EN 7
43 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
45 static int baltos_set_console(void)
50 for (i = 0; i < 4; i++) {
51 sprintf(buf, "dip_s%d", i + 1);
53 if (gpio_request(DIP_S1 + i, buf)) {
54 printf("failed to export GPIO %d\n", DIP_S1 + i);
58 if (gpio_direction_input(DIP_S1 + i)) {
59 printf("failed to set GPIO %d direction\n", DIP_S1 + i);
63 val = gpio_get_value(DIP_S1 + i);
67 printf("DIPs: 0x%1x\n", (~dips) & 0xf);
69 if ((dips & 0xf) == 0xe)
70 env_set("console", "ttyUSB0,115200n8");
75 static int read_eeprom(BSP_VS_HWPARAM *header)
79 /* Check if baseboard eeprom is available */
80 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
81 puts("Could not probe the EEPROM; something fundamentally "
82 "wrong on the I2C bus.\n");
86 /* read the eeprom using i2c */
87 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
88 sizeof(BSP_VS_HWPARAM))) {
89 puts("Could not read the EEPROM; something fundamentally"
90 " wrong on the I2C bus.\n");
94 if (header->Magic != 0xDEADBEEF) {
96 printf("Incorrect magic number (0x%x) in EEPROM\n",
99 /* fill default values */
100 header->SystemId = 211;
101 header->MAC1[0] = 0x00;
102 header->MAC1[1] = 0x00;
103 header->MAC1[2] = 0x00;
104 header->MAC1[3] = 0x00;
105 header->MAC1[4] = 0x00;
106 header->MAC1[5] = 0x01;
108 header->MAC2[0] = 0x00;
109 header->MAC2[1] = 0x00;
110 header->MAC2[2] = 0x00;
111 header->MAC2[3] = 0x00;
112 header->MAC2[4] = 0x00;
113 header->MAC2[5] = 0x02;
115 header->MAC3[0] = 0x00;
116 header->MAC3[1] = 0x00;
117 header->MAC3[2] = 0x00;
118 header->MAC3[3] = 0x00;
119 header->MAC3[4] = 0x00;
120 header->MAC3[5] = 0x03;
126 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
128 static const struct ddr_data ddr3_baltos_data = {
129 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
130 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
131 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
132 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
135 static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
136 .cmd0csratio = MT41K256M16HA125E_RATIO,
137 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
139 .cmd1csratio = MT41K256M16HA125E_RATIO,
140 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
142 .cmd2csratio = MT41K256M16HA125E_RATIO,
143 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
146 static struct emif_regs ddr3_baltos_emif_reg_data = {
147 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
148 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
149 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
150 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
151 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
152 .zq_config = MT41K256M16HA125E_ZQ_CFG,
153 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
156 #ifdef CONFIG_SPL_OS_BOOT
157 int spl_start_uboot(void)
159 /* break into full u-boot on 'c' */
160 return (serial_tstc() && serial_getc() == 'c');
164 #define OSC (V_OSCK/1000000)
165 const struct dpll_params dpll_ddr = {
166 266, OSC-1, 1, -1, -1, -1, -1};
167 const struct dpll_params dpll_ddr_evm_sk = {
168 303, OSC-1, 1, -1, -1, -1, -1};
169 const struct dpll_params dpll_ddr_baltos = {
170 400, OSC-1, 1, -1, -1, -1, -1};
172 void am33xx_spl_board_init(void)
177 /* Get the frequency */
178 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
181 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
182 * MPU frequencies we support we use a CORE voltage of
183 * 1.1375V. For MPU voltage we need to switch based on
184 * the frequency we are running at.
188 printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
190 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
191 puts("i2c: cannot access TPS65910\n");
196 * Depending on MPU clock and PG we will need a different
197 * VDD to drive at that speed.
199 sil_rev = readl(&cdev->deviceid) >> 28;
200 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
203 /* Tell the TPS65910 to use i2c */
204 tps65910_set_i2c_control();
206 /* First update MPU voltage. */
207 if (tps65910_voltage_update(MPU, mpu_vdd))
210 /* Second, update the CORE voltage. */
211 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
214 /* Set CORE Frequencies to OPP100 */
215 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
217 /* Set MPU Frequency to what we detected now that voltages are set */
218 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
220 writel(0x000010ff, PRM_DEVICE_INST + 4);
223 const struct dpll_params *get_dpll_ddr_params(void)
225 enable_i2c1_pin_mux();
228 return &dpll_ddr_baltos;
231 void set_uart_mux_conf(void)
233 enable_uart0_pin_mux();
236 void set_mux_conf_regs(void)
238 enable_board_pin_mux();
241 const struct ctrl_ioregs ioregs_baltos = {
242 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
243 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
244 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
245 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
246 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
249 void sdram_init(void)
251 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
252 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
254 config_ddr(400, &ioregs_baltos,
256 &ddr3_baltos_cmd_ctrl_data,
257 &ddr3_baltos_emif_reg_data, 0);
262 * Basic board specific setup. Pinmux has been handled already.
266 #if defined(CONFIG_HW_WATCHDOG)
270 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
271 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
277 int ft_board_setup(void *blob, bd_t *bd)
280 unsigned char mac_addr[6];
281 BSP_VS_HWPARAM header;
283 /* get production data */
284 if (read_eeprom(&header))
288 mac_addr[0] = header.MAC1[0];
289 mac_addr[1] = header.MAC1[1];
290 mac_addr[2] = header.MAC1[2];
291 mac_addr[3] = header.MAC1[3];
292 mac_addr[4] = header.MAC1[4];
293 mac_addr[5] = header.MAC1[5];
296 node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
298 printf("no /soc/fman/ethernet path offset\n");
302 ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
304 printf("error setting local-mac-address property\n");
309 mac_addr[0] = header.MAC2[0];
310 mac_addr[1] = header.MAC2[1];
311 mac_addr[2] = header.MAC2[2];
312 mac_addr[3] = header.MAC2[3];
313 mac_addr[4] = header.MAC2[4];
314 mac_addr[5] = header.MAC2[5];
316 node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
318 printf("no /soc/fman/ethernet path offset\n");
322 ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
324 printf("error setting local-mac-address property\n");
328 printf("\nFDT was successfully setup\n");
333 static struct module_pin_mux pcie_sw_pin_mux[] = {
334 {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */
338 static struct module_pin_mux dip_pin_mux[] = {
339 {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
340 {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
341 {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
342 {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
346 #ifdef CONFIG_BOARD_LATE_INIT
347 int board_late_init(void)
349 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
350 BSP_VS_HWPARAM header;
353 /* get production data */
354 if (read_eeprom(&header)) {
355 strcpy(model, "211");
357 sprintf(model, "%d", header.SystemId);
358 if (header.SystemId == 215) {
359 configure_module_pin_mux(dip_pin_mux);
360 baltos_set_console();
364 /* turn power for the mPCIe slot */
365 configure_module_pin_mux(pcie_sw_pin_mux);
366 if (gpio_request(MPCIE_SW, "mpcie_sw")) {
367 printf("failed to export GPIO %d\n", MPCIE_SW);
370 if (gpio_direction_output(MPCIE_SW, 1)) {
371 printf("failed to set GPIO %d direction\n", MPCIE_SW);
375 env_set("board_name", model);
382 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
383 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
384 static void cpsw_control(int enabled)
386 /* VTP can be added here */
391 static struct cpsw_slave_data cpsw_slaves[] = {
393 .slave_reg_ofs = 0x208,
394 .sliver_reg_ofs = 0xd80,
398 .slave_reg_ofs = 0x308,
399 .sliver_reg_ofs = 0xdc0,
404 static struct cpsw_platform_data cpsw_data = {
405 .mdio_base = CPSW_MDIO_BASE,
406 .cpsw_base = CPSW_BASE,
409 .cpdma_reg_ofs = 0x800,
411 .slave_data = cpsw_slaves,
413 .ale_reg_ofs = 0xd00,
415 .host_port_reg_ofs = 0x108,
416 .hw_stats_reg_ofs = 0x900,
417 .bd_ram_ofs = 0x2000,
418 .mac_control = (1 << 5),
419 .control = cpsw_control,
421 .version = CPSW_CTRL_VERSION_2,
425 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
426 && defined(CONFIG_SPL_BUILD)) || \
427 ((defined(CONFIG_DRIVER_TI_CPSW) || \
428 defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
429 !defined(CONFIG_SPL_BUILD))
430 int board_eth_init(bd_t *bis)
434 uint32_t mac_hi, mac_lo;
437 * Note here that we're using CPSW1 since that has a 1Gbit PHY while
438 * CSPW0 has a 100Mbit PHY.
440 * On product, CPSW1 maps to port labeled WAN.
443 /* try reading mac address from efuse */
444 mac_lo = readl(&cdev->macid1l);
445 mac_hi = readl(&cdev->macid1h);
446 mac_addr[0] = mac_hi & 0xFF;
447 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
448 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
449 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
450 mac_addr[4] = mac_lo & 0xFF;
451 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
453 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
454 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
455 if (!env_get("ethaddr")) {
456 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
458 if (is_valid_ethaddr(mac_addr))
459 eth_env_set_enetaddr("ethaddr", mac_addr);
462 #ifdef CONFIG_DRIVER_TI_CPSW
463 writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
464 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
465 rv = cpsw_register(&cpsw_data);
467 printf("Error %d registering CPSW switch\n", rv);
474 * CPSW RGMII Internal Delay Mode is not supported in all PVT
475 * operating points. So we must set the TX clock delay feature
476 * in the AR8051 PHY. Since we only support a single ethernet
477 * device in U-Boot, we only do this for the first instance.
479 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
480 #define AR8051_PHY_DEBUG_DATA_REG 0x1e
481 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
482 #define AR8051_RGMII_TX_CLK_DLY 0x100
484 devname = miiphy_get_current_dev();
486 miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
487 AR8051_DEBUG_RGMII_CLK_DLY_REG);
488 miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
489 AR8051_RGMII_TX_CLK_DLY);