board/vscom/baltos/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM335X based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <spl.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/omap.h>
  17 #include <asm/arch/ddr_defs.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/mmc_host_def.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mem.h>
  23 #include <asm/arch/mux.h>
  24 #include <asm/io.h>
  25 #include <asm/emif.h>
  26 #include <asm/gpio.h>
  27 #include <i2c.h>
  28 #include <miiphy.h>
  29 #include <cpsw.h>
  30 #include <power/tps65217.h>
  31 #include <power/tps65910.h>
  32 #include <environment.h>
  33 #include <watchdog.h>
  34 #include "board.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 /* GPIO that controls power to DDR on EVM-SK */
  39 #define GPIO_DDR_VTT_EN         7
  40 #define DIP_S1                  44
  41
  42 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  43
  44 static int baltos_set_console(void)
  45 {
  46         int val, i, dips = 0;
  47         char buf[7];
  48
  49         for (i = 0; i < 4; i++) {
  50                 sprintf(buf, "dip_s%d", i + 1);
  51
  52                 if (gpio_request(DIP_S1 + i, buf)) {
  53                         printf("failed to export GPIO %d\n", DIP_S1 + i);
  54                         return 0;
  55                 }
  56
  57                 if (gpio_direction_input(DIP_S1 + i)) {
  58                         printf("failed to set GPIO %d direction\n", DIP_S1 + i);
  59                         return 0;
  60                 }
  61
  62                 val = gpio_get_value(DIP_S1 + i);
  63                 dips |= val << i;
  64         }
  65
  66         printf("DIPs: 0x%1x\n", (~dips) & 0xf);
  67
  68         if ((dips & 0xf) == 0xe)
  69                 setenv("console", "ttyUSB0,115200n8");
  70
  71         return 0;
  72 }
  73
  74 static int read_eeprom(BSP_VS_HWPARAM *header)
  75 {
  76         i2c_set_bus_num(1);
  77
  78         /* Check if baseboard eeprom is available */
  79         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  80                 puts("Could not probe the EEPROM; something fundamentally "
  81                         "wrong on the I2C bus.\n");
  82                 return -ENODEV;
  83         }
  84
  85         /* read the eeprom using i2c */
  86         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  87                      sizeof(BSP_VS_HWPARAM))) {
  88                 puts("Could not read the EEPROM; something fundamentally"
  89                         " wrong on the I2C bus.\n");
  90                 return -EIO;
  91         }
  92
  93         if (header->Magic != 0xDEADBEEF) {
  94
  95                 printf("Incorrect magic number (0x%x) in EEPROM\n",
  96                                 header->Magic);
  97
  98                 /* fill default values */
  99                 header->SystemId = 211;
 100                 header->MAC1[0] = 0x00;
 101                 header->MAC1[1] = 0x00;
 102                 header->MAC1[2] = 0x00;
 103                 header->MAC1[3] = 0x00;
 104                 header->MAC1[4] = 0x00;
 105                 header->MAC1[5] = 0x01;
 106
 107                 header->MAC2[0] = 0x00;
 108                 header->MAC2[1] = 0x00;
 109                 header->MAC2[2] = 0x00;
 110                 header->MAC2[3] = 0x00;
 111                 header->MAC2[4] = 0x00;
 112                 header->MAC2[5] = 0x02;
 113
 114                 header->MAC3[0] = 0x00;
 115                 header->MAC3[1] = 0x00;
 116                 header->MAC3[2] = 0x00;
 117                 header->MAC3[3] = 0x00;
 118                 header->MAC3[4] = 0x00;
 119                 header->MAC3[5] = 0x03;
 120         }
 121
 122         return 0;
 123 }
 124
 125 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
 126
 127 static const struct ddr_data ddr3_baltos_data = {
 128         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 129         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 130         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 131         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 132 };
 133
 134 static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
 135         .cmd0csratio = MT41K256M16HA125E_RATIO,
 136         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 137
 138         .cmd1csratio = MT41K256M16HA125E_RATIO,
 139         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 140
 141         .cmd2csratio = MT41K256M16HA125E_RATIO,
 142         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 143 };
 144
 145 static struct emif_regs ddr3_baltos_emif_reg_data = {
 146         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 147         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 148         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 149         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 150         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 151         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 152         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 153 };
 154
 155 #ifdef CONFIG_SPL_OS_BOOT
 156 int spl_start_uboot(void)
 157 {
 158         /* break into full u-boot on 'c' */
 159         return (serial_tstc() && serial_getc() == 'c');
 160 }
 161 #endif
 162
 163 #define OSC     (V_OSCK/1000000)
 164 const struct dpll_params dpll_ddr = {
 165                 266, OSC-1, 1, -1, -1, -1, -1};
 166 const struct dpll_params dpll_ddr_evm_sk = {
 167                 303, OSC-1, 1, -1, -1, -1, -1};
 168 const struct dpll_params dpll_ddr_baltos = {
 169                 400, OSC-1, 1, -1, -1, -1, -1};
 170
 171 void am33xx_spl_board_init(void)
 172 {
 173         int mpu_vdd;
 174         int sil_rev;
 175
 176         /* Get the frequency */
 177         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 178
 179         /*
 180          * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 181          * MPU frequencies we support we use a CORE voltage of
 182          * 1.1375V.  For MPU voltage we need to switch based on
 183          * the frequency we are running at.
 184          */
 185         i2c_set_bus_num(1);
 186
 187         if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
 188                 puts("i2c: cannot access TPS65910\n");
 189                 return;
 190         }
 191
 192         /*
 193          * Depending on MPU clock and PG we will need a different
 194          * VDD to drive at that speed.
 195          */
 196         sil_rev = readl(&cdev->deviceid) >> 28;
 197         mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
 198                                               dpll_mpu_opp100.m);
 199
 200         /* Tell the TPS65910 to use i2c */
 201         tps65910_set_i2c_control();
 202
 203         /* First update MPU voltage. */
 204         if (tps65910_voltage_update(MPU, mpu_vdd))
 205                 return;
 206
 207         /* Second, update the CORE voltage. */
 208         if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
 209                 return;
 210
 211         /* Set CORE Frequencies to OPP100 */
 212         do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 213
 214         /* Set MPU Frequency to what we detected now that voltages are set */
 215         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 216
 217         writel(0x000010ff, PRM_DEVICE_INST + 4);
 218 }
 219
 220 const struct dpll_params *get_dpll_ddr_params(void)
 221 {
 222         enable_i2c1_pin_mux();
 223         i2c_set_bus_num(1);
 224
 225         return &dpll_ddr_baltos;
 226 }
 227
 228 void set_uart_mux_conf(void)
 229 {
 230         enable_uart0_pin_mux();
 231 }
 232
 233 void set_mux_conf_regs(void)
 234 {
 235         enable_board_pin_mux();
 236 }
 237
 238 const struct ctrl_ioregs ioregs_baltos = {
 239         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 240         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 241         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 242         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 243         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 244 };
 245
 246 void sdram_init(void)
 247 {
 248         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 249         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 250
 251         config_ddr(400, &ioregs_baltos,
 252                    &ddr3_baltos_data,
 253                    &ddr3_baltos_cmd_ctrl_data,
 254                    &ddr3_baltos_emif_reg_data, 0);
 255 }
 256 #endif
 257
 258 /*
 259  * Basic board specific setup.  Pinmux has been handled already.
 260  */
 261 int board_init(void)
 262 {
 263 #if defined(CONFIG_HW_WATCHDOG)
 264         hw_watchdog_init();
 265 #endif
 266
 267         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 268 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 269         gpmc_init();
 270 #endif
 271         return 0;
 272 }
 273
 274 int ft_board_setup(void *blob, bd_t *bd)
 275 {
 276         int node, ret;
 277         unsigned char mac_addr[6];
 278         BSP_VS_HWPARAM header;
 279
 280         /* get production data */
 281         if (read_eeprom(&header))
 282                 return 0;
 283
 284         /* setup MAC1 */
 285         mac_addr[0] = header.MAC1[0];
 286         mac_addr[1] = header.MAC1[1];
 287         mac_addr[2] = header.MAC1[2];
 288         mac_addr[3] = header.MAC1[3];
 289         mac_addr[4] = header.MAC1[4];
 290         mac_addr[5] = header.MAC1[5];
 291
 292
 293         node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
 294         if (node < 0) {
 295                 printf("no /soc/fman/ethernet path offset\n");
 296                 return -ENODEV;
 297         }
 298
 299         ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
 300         if (ret) {
 301                 printf("error setting local-mac-address property\n");
 302                 return -ENODEV;
 303         }
 304
 305         /* setup MAC2 */
 306         mac_addr[0] = header.MAC2[0];
 307         mac_addr[1] = header.MAC2[1];
 308         mac_addr[2] = header.MAC2[2];
 309         mac_addr[3] = header.MAC2[3];
 310         mac_addr[4] = header.MAC2[4];
 311         mac_addr[5] = header.MAC2[5];
 312
 313         node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
 314         if (node < 0) {
 315                 printf("no /soc/fman/ethernet path offset\n");
 316                 return -ENODEV;
 317         }
 318
 319         ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
 320         if (ret) {
 321                 printf("error setting local-mac-address property\n");
 322                 return -ENODEV;
 323         }
 324
 325         printf("\nFDT was successfully setup\n");
 326
 327         return 0;
 328 }
 329
 330 static struct module_pin_mux dip_pin_mux[] = {
 331         {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )},     /* GPIO1_12 */
 332         {OFFSET(gpmc_ad13), (MODE(7)  | RXACTIVE )},    /* GPIO1_13 */
 333         {OFFSET(gpmc_ad14), (MODE(7)  | RXACTIVE )},    /* GPIO1_14 */
 334         {OFFSET(gpmc_ad15), (MODE(7)  | RXACTIVE )},    /* GPIO1_15 */
 335         {-1},
 336 };
 337
 338 #ifdef CONFIG_BOARD_LATE_INIT
 339 int board_late_init(void)
 340 {
 341 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 342         BSP_VS_HWPARAM header;
 343         char model[4];
 344
 345         /* get production data */
 346         if (read_eeprom(&header)) {
 347                 sprintf(model, "211");
 348         } else {
 349                 sprintf(model, "%d", header.SystemId);
 350                 if (header.SystemId == 215) {
 351                         configure_module_pin_mux(dip_pin_mux);
 352                         baltos_set_console();
 353                 }
 354         }
 355         setenv("board_name", model);
 356 #endif
 357
 358         return 0;
 359 }
 360 #endif
 361
 362 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 363         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 364 static void cpsw_control(int enabled)
 365 {
 366         /* VTP can be added here */
 367
 368         return;
 369 }
 370
 371 static struct cpsw_slave_data cpsw_slaves[] = {
 372         {
 373                 .slave_reg_ofs  = 0x208,
 374                 .sliver_reg_ofs = 0xd80,
 375                 .phy_addr       = 0,
 376         },
 377         {
 378                 .slave_reg_ofs  = 0x308,
 379                 .sliver_reg_ofs = 0xdc0,
 380                 .phy_addr       = 7,
 381         },
 382 };
 383
 384 static struct cpsw_platform_data cpsw_data = {
 385         .mdio_base              = CPSW_MDIO_BASE,
 386         .cpsw_base              = CPSW_BASE,
 387         .mdio_div               = 0xff,
 388         .channels               = 8,
 389         .cpdma_reg_ofs          = 0x800,
 390         .slaves                 = 2,
 391         .slave_data             = cpsw_slaves,
 392         .active_slave           = 1,
 393         .ale_reg_ofs            = 0xd00,
 394         .ale_entries            = 1024,
 395         .host_port_reg_ofs      = 0x108,
 396         .hw_stats_reg_ofs       = 0x900,
 397         .bd_ram_ofs             = 0x2000,
 398         .mac_control            = (1 << 5),
 399         .control                = cpsw_control,
 400         .host_port_num          = 0,
 401         .version                = CPSW_CTRL_VERSION_2,
 402 };
 403 #endif
 404
 405 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
 406                 && defined(CONFIG_SPL_BUILD)) || \
 407         ((defined(CONFIG_DRIVER_TI_CPSW) || \
 408           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
 409          !defined(CONFIG_SPL_BUILD))
 410 int board_eth_init(bd_t *bis)
 411 {
 412         int rv, n = 0;
 413         uint8_t mac_addr[6];
 414         uint32_t mac_hi, mac_lo;
 415         __maybe_unused struct am335x_baseboard_id header;
 416
 417         /*
 418          * Note here that we're using CPSW1 since that has a 1Gbit PHY while
 419          * CSPW0 has a 100Mbit PHY.
 420          *
 421          * On product, CPSW1 maps to port labeled WAN.
 422          */
 423
 424         /* try reading mac address from efuse */
 425         mac_lo = readl(&cdev->macid1l);
 426         mac_hi = readl(&cdev->macid1h);
 427         mac_addr[0] = mac_hi & 0xFF;
 428         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 429         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 430         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 431         mac_addr[4] = mac_lo & 0xFF;
 432         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 433
 434 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 435         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 436         if (!getenv("ethaddr")) {
 437                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 438
 439                 if (is_valid_ethaddr(mac_addr))
 440                         eth_setenv_enetaddr("ethaddr", mac_addr);
 441         }
 442
 443 #ifdef CONFIG_DRIVER_TI_CPSW
 444         writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
 445         cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
 446         rv = cpsw_register(&cpsw_data);
 447         if (rv < 0)
 448                 printf("Error %d registering CPSW switch\n", rv);
 449         else
 450                 n += rv;
 451 #endif
 452
 453         /*
 454          *
 455          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 456          * operating points.  So we must set the TX clock delay feature
 457          * in the AR8051 PHY.  Since we only support a single ethernet
 458          * device in U-Boot, we only do this for the first instance.
 459          */
 460 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 461 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 462 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 463 #define AR8051_RGMII_TX_CLK_DLY         0x100
 464         const char *devname;
 465         devname = miiphy_get_current_dev();
 466
 467         miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
 468                         AR8051_DEBUG_RGMII_CLK_DLY_REG);
 469         miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
 470                         AR8051_RGMII_TX_CLK_DLY);
 471 #endif
 472         return n;
 473 }
 474 #endif