1 // SPDX-License-Identifier: GPL-2.0+
5 * Board functions for TI AM335X based boards
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
16 #include <linux/libfdt.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/omap.h>
21 #include <asm/arch/ddr_defs.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/mmc_host_def.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/mem.h>
27 #include <asm/arch/mux.h>
34 #include <power/tps65910.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 /* GPIO that controls DIP switch and mPCIe slot */
44 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
46 static int baltos_set_console(void)
51 for (i = 0; i < 4; i++) {
52 sprintf(buf, "dip_s%d", i + 1);
54 if (gpio_request(DIP_S1 + i, buf)) {
55 printf("failed to export GPIO %d\n", DIP_S1 + i);
59 if (gpio_direction_input(DIP_S1 + i)) {
60 printf("failed to set GPIO %d direction\n", DIP_S1 + i);
64 val = gpio_get_value(DIP_S1 + i);
68 printf("DIPs: 0x%1x\n", (~dips) & 0xf);
70 if ((dips & 0xf) == 0xe)
71 env_set("console", "ttyUSB0,115200n8");
76 static int read_eeprom(BSP_VS_HWPARAM *header)
80 /* Check if baseboard eeprom is available */
81 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
82 puts("Could not probe the EEPROM; something fundamentally "
83 "wrong on the I2C bus.\n");
87 /* read the eeprom using i2c */
88 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
89 sizeof(BSP_VS_HWPARAM))) {
90 puts("Could not read the EEPROM; something fundamentally"
91 " wrong on the I2C bus.\n");
95 if (header->Magic != 0xDEADBEEF) {
97 printf("Incorrect magic number (0x%x) in EEPROM\n",
100 /* fill default values */
101 header->SystemId = 211;
102 header->MAC1[0] = 0x00;
103 header->MAC1[1] = 0x00;
104 header->MAC1[2] = 0x00;
105 header->MAC1[3] = 0x00;
106 header->MAC1[4] = 0x00;
107 header->MAC1[5] = 0x01;
109 header->MAC2[0] = 0x00;
110 header->MAC2[1] = 0x00;
111 header->MAC2[2] = 0x00;
112 header->MAC2[3] = 0x00;
113 header->MAC2[4] = 0x00;
114 header->MAC2[5] = 0x02;
116 header->MAC3[0] = 0x00;
117 header->MAC3[1] = 0x00;
118 header->MAC3[2] = 0x00;
119 header->MAC3[3] = 0x00;
120 header->MAC3[4] = 0x00;
121 header->MAC3[5] = 0x03;
127 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
129 static const struct ddr_data ddr3_baltos_data = {
130 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
131 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
132 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
133 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
136 static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
137 .cmd0csratio = MT41K256M16HA125E_RATIO,
138 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
140 .cmd1csratio = MT41K256M16HA125E_RATIO,
141 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
143 .cmd2csratio = MT41K256M16HA125E_RATIO,
144 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
147 static struct emif_regs ddr3_baltos_emif_reg_data = {
148 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
149 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
150 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
151 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
152 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
153 .zq_config = MT41K256M16HA125E_ZQ_CFG,
154 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
157 #ifdef CONFIG_SPL_OS_BOOT
158 int spl_start_uboot(void)
160 /* break into full u-boot on 'c' */
161 return (serial_tstc() && serial_getc() == 'c');
165 #define OSC (V_OSCK/1000000)
166 const struct dpll_params dpll_ddr = {
167 266, OSC-1, 1, -1, -1, -1, -1};
168 const struct dpll_params dpll_ddr_evm_sk = {
169 303, OSC-1, 1, -1, -1, -1, -1};
170 const struct dpll_params dpll_ddr_baltos = {
171 400, OSC-1, 1, -1, -1, -1, -1};
173 void am33xx_spl_board_init(void)
178 /* Get the frequency */
179 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
182 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
183 * MPU frequencies we support we use a CORE voltage of
184 * 1.1375V. For MPU voltage we need to switch based on
185 * the frequency we are running at.
189 printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
191 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
192 puts("i2c: cannot access TPS65910\n");
197 * Depending on MPU clock and PG we will need a different
198 * VDD to drive at that speed.
200 sil_rev = readl(&cdev->deviceid) >> 28;
201 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
204 /* Tell the TPS65910 to use i2c */
205 tps65910_set_i2c_control();
207 /* First update MPU voltage. */
208 if (tps65910_voltage_update(MPU, mpu_vdd))
211 /* Second, update the CORE voltage. */
212 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
215 /* Set CORE Frequencies to OPP100 */
216 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
218 /* Set MPU Frequency to what we detected now that voltages are set */
219 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
221 writel(0x000010ff, PRM_DEVICE_INST + 4);
224 const struct dpll_params *get_dpll_ddr_params(void)
226 enable_i2c1_pin_mux();
229 return &dpll_ddr_baltos;
232 void set_uart_mux_conf(void)
234 enable_uart0_pin_mux();
237 void set_mux_conf_regs(void)
239 enable_board_pin_mux();
242 const struct ctrl_ioregs ioregs_baltos = {
243 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
244 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
245 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
246 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
247 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
250 void sdram_init(void)
252 config_ddr(400, &ioregs_baltos,
254 &ddr3_baltos_cmd_ctrl_data,
255 &ddr3_baltos_emif_reg_data, 0);
260 * Basic board specific setup. Pinmux has been handled already.
264 #if defined(CONFIG_HW_WATCHDOG)
268 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
269 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
275 int ft_board_setup(void *blob, bd_t *bd)
278 unsigned char mac_addr[6];
279 BSP_VS_HWPARAM header;
281 /* get production data */
282 if (read_eeprom(&header))
286 mac_addr[0] = header.MAC1[0];
287 mac_addr[1] = header.MAC1[1];
288 mac_addr[2] = header.MAC1[2];
289 mac_addr[3] = header.MAC1[3];
290 mac_addr[4] = header.MAC1[4];
291 mac_addr[5] = header.MAC1[5];
294 node = fdt_path_offset(blob, "ethernet0");
296 printf("no ethernet0 path offset\n");
300 ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
302 printf("error setting mac-address property\n");
307 mac_addr[0] = header.MAC2[0];
308 mac_addr[1] = header.MAC2[1];
309 mac_addr[2] = header.MAC2[2];
310 mac_addr[3] = header.MAC2[3];
311 mac_addr[4] = header.MAC2[4];
312 mac_addr[5] = header.MAC2[5];
314 node = fdt_path_offset(blob, "ethernet1");
316 printf("no ethernet1 path offset\n");
320 ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
322 printf("error setting mac-address property\n");
326 printf("\nFDT was successfully setup\n");
331 static struct module_pin_mux pcie_sw_pin_mux[] = {
332 {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */
336 static struct module_pin_mux dip_pin_mux[] = {
337 {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
338 {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
339 {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
340 {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
344 #ifdef CONFIG_BOARD_LATE_INIT
345 int board_late_init(void)
347 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
348 BSP_VS_HWPARAM header;
351 /* get production data */
352 if (read_eeprom(&header)) {
353 strcpy(model, "211");
355 sprintf(model, "%d", header.SystemId);
356 if (header.SystemId == 215) {
357 configure_module_pin_mux(dip_pin_mux);
358 baltos_set_console();
362 /* turn power for the mPCIe slot */
363 configure_module_pin_mux(pcie_sw_pin_mux);
364 if (gpio_request(MPCIE_SW, "mpcie_sw")) {
365 printf("failed to export GPIO %d\n", MPCIE_SW);
368 if (gpio_direction_output(MPCIE_SW, 1)) {
369 printf("failed to set GPIO %d direction\n", MPCIE_SW);
373 env_set("board_name", model);
380 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
381 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
382 static void cpsw_control(int enabled)
384 /* VTP can be added here */
389 static struct cpsw_slave_data cpsw_slaves[] = {
391 .slave_reg_ofs = 0x208,
392 .sliver_reg_ofs = 0xd80,
396 .slave_reg_ofs = 0x308,
397 .sliver_reg_ofs = 0xdc0,
402 static struct cpsw_platform_data cpsw_data = {
403 .mdio_base = CPSW_MDIO_BASE,
404 .cpsw_base = CPSW_BASE,
407 .cpdma_reg_ofs = 0x800,
409 .slave_data = cpsw_slaves,
411 .ale_reg_ofs = 0xd00,
413 .host_port_reg_ofs = 0x108,
414 .hw_stats_reg_ofs = 0x900,
415 .bd_ram_ofs = 0x2000,
416 .mac_control = (1 << 5),
417 .control = cpsw_control,
419 .version = CPSW_CTRL_VERSION_2,
423 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
424 && defined(CONFIG_SPL_BUILD)) || \
425 ((defined(CONFIG_DRIVER_TI_CPSW) || \
426 defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
427 !defined(CONFIG_SPL_BUILD))
428 int board_eth_init(bd_t *bis)
432 uint32_t mac_hi, mac_lo;
435 * Note here that we're using CPSW1 since that has a 1Gbit PHY while
436 * CSPW0 has a 100Mbit PHY.
438 * On product, CPSW1 maps to port labeled WAN.
441 /* try reading mac address from efuse */
442 mac_lo = readl(&cdev->macid1l);
443 mac_hi = readl(&cdev->macid1h);
444 mac_addr[0] = mac_hi & 0xFF;
445 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
446 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
447 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
448 mac_addr[4] = mac_lo & 0xFF;
449 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
451 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
452 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
453 if (!env_get("ethaddr")) {
454 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
456 if (is_valid_ethaddr(mac_addr))
457 eth_env_set_enetaddr("ethaddr", mac_addr);
460 #ifdef CONFIG_DRIVER_TI_CPSW
461 writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
462 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
463 rv = cpsw_register(&cpsw_data);
465 printf("Error %d registering CPSW switch\n", rv);
472 * CPSW RGMII Internal Delay Mode is not supported in all PVT
473 * operating points. So we must set the TX clock delay feature
474 * in the AR8051 PHY. Since we only support a single ethernet
475 * device in U-Boot, we only do this for the first instance.
477 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
478 #define AR8051_PHY_DEBUG_DATA_REG 0x1e
479 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
480 #define AR8051_RGMII_TX_CLK_DLY 0x100
482 devname = miiphy_get_current_dev();
484 miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
485 AR8051_DEBUG_RGMII_CLK_DLY_REG);
486 miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
487 AR8051_RGMII_TX_CLK_DLY);