board/variscite/dart_6ul/dart_6ul.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015-2019 Variscite Ltd.
   4  * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
   5  */
   6
   7 #include <init.h>
   8 #include <net.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/mach-imx/iomux-v3.h>
  14 #include <asm/mach-imx/mxc_i2c.h>
  15 #include <dm.h>
  16 #include <fsl_esdhc_imx.h>
  17 #include <i2c_eeprom.h>
  18 #include <linux/bitops.h>
  19 #include <malloc.h>
  20 #include <miiphy.h>
  21 #include <netdev.h>
  22 #include <usb.h>
  23 #include <usb/ehci-ci.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 int dram_init(void)
  28 {
  29         gd->ram_size = imx_ddr_size();
  30
  31         return 0;
  32 }
  33
  34 #ifdef CONFIG_NAND_MXS
  35 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  36 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  37                         PAD_CTL_SRE_FAST)
  38 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  39 static iomux_v3_cfg_t const nand_pads[] = {
  40         MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  41         MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  42         MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  43         MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  44         MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  45         MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  46         MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  47         MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  48         MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  49         MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  50         MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  51         MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  52         MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  53         MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  54         MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  55         MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  56 };
  57
  58 static void setup_gpmi_nand(void)
  59 {
  60         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  61
  62         /* config gpmi nand iomux */
  63         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  64
  65         clrbits_le32(&mxc_ccm->CCGR4,
  66                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  67                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  68                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  69                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  70                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  71
  72         /*
  73          * config gpmi and bch clock to 100 MHz
  74          * bch/gpmi select PLL2 PFD2 400M
  75          * 100M = 400M / 4
  76          */
  77         clrbits_le32(&mxc_ccm->cscmr1,
  78                      MXC_CCM_CSCMR1_BCH_CLK_SEL |
  79                      MXC_CCM_CSCMR1_GPMI_CLK_SEL);
  80         clrsetbits_le32(&mxc_ccm->cscdr1,
  81                         MXC_CCM_CSCDR1_BCH_PODF_MASK |
  82                         MXC_CCM_CSCDR1_GPMI_PODF_MASK,
  83                         (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
  84                         (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
  85
  86         /* enable gpmi and bch clock gating */
  87         setbits_le32(&mxc_ccm->CCGR4,
  88                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  89                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  90                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  91                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  92                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  93
  94         /* enable apbh clock gating */
  95         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  96 }
  97 #endif
  98
  99 #ifdef CONFIG_FEC_MXC
 100 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
 101 #define ENET_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE       | \
 102                            PAD_CTL_SPEED_HIGH  | PAD_CTL_DSE_48ohm | \
 103                            PAD_CTL_SRE_FAST)
 104 #define MDIO_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE      | \
 105                            PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | \
 106                            PAD_CTL_ODE)
 107 /*
 108  * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
 109  * be used for ENET1 or ENET2, cannot be used for both.
 110  */
 111 static iomux_v3_cfg_t const fec1_pads[] = {
 112         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
 113         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 114         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 115         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 116         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 117         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 118         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 119         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
 121         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 122 };
 123
 124 static iomux_v3_cfg_t const fec2_pads[] = {
 125         MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
 126         MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 127         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 128         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 129         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 130         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 131         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 132         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 133         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
 134         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 135 };
 136
 137 static void setup_iomux_fec(int fec_id)
 138 {
 139         if (fec_id == 0)
 140                 imx_iomux_v3_setup_multiple_pads(fec1_pads,
 141                                                  ARRAY_SIZE(fec1_pads));
 142         else
 143                 imx_iomux_v3_setup_multiple_pads(fec2_pads,
 144                                                  ARRAY_SIZE(fec2_pads));
 145 }
 146
 147 int board_eth_init(struct bd_info *bis)
 148 {
 149         int ret = 0;
 150
 151         ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
 152                                       CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 153
 154 #if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER)
 155         /* USB Ethernet Gadget */
 156         usb_eth_initialize(bis);
 157 #endif
 158         return ret;
 159 }
 160
 161 static int setup_fec(int fec_id)
 162 {
 163         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 164         int ret;
 165
 166         if (fec_id == 0) {
 167                 /*
 168                  * Use 50M anatop loopback REF_CLK1 for ENET1,
 169                  * clear gpr1[13], set gpr1[17].
 170                  */
 171                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
 172                                 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
 173         } else {
 174                 /*
 175                  * Use 50M anatop loopback REF_CLK2 for ENET2,
 176                  * clear gpr1[14], set gpr1[18].
 177                  */
 178                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
 179                                 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 180         }
 181
 182         ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
 183         if (ret)
 184                 return ret;
 185
 186         enable_enet_clk(1);
 187
 188         return 0;
 189 }
 190
 191 int board_phy_config(struct phy_device *phydev)
 192 {
 193         /*
 194          * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
 195          * 50 MHz RMII clock mode.
 196          */
 197         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
 198
 199         if (phydev->drv->config)
 200                 phydev->drv->config(phydev);
 201
 202         return 0;
 203 }
 204 #endif /* CONFIG_FEC_MXC */
 205
 206 int board_early_init_f(void)
 207 {
 208         setup_iomux_fec(CONFIG_FEC_ENET_DEV);
 209
 210         return 0;
 211 }
 212
 213 int board_init(void)
 214 {
 215         /* Address of boot parameters */
 216         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 217
 218 #ifdef CONFIG_FEC_MXC
 219         setup_fec(CONFIG_FEC_ENET_DEV);
 220 #endif
 221
 222 #ifdef CONFIG_NAND_MXS
 223         setup_gpmi_nand();
 224 #endif
 225         return 0;
 226 }
 227
 228 /* length of strings stored in the eeprom */
 229 #define DART6UL_PN_LEN   16
 230 #define DART6UL_ASSY_LEN 16
 231 #define DART6UL_DATE_LEN 12
 232
 233 /* eeprom content, 512 bytes */
 234 struct dart6ul_info {
 235         u32 magic;
 236         u8 partnumber[DART6UL_PN_LEN];
 237         u8 assy[DART6UL_ASSY_LEN];
 238         u8 date[DART6UL_DATE_LEN];
 239         u32 custom_addr_val[32];
 240         struct cmd {
 241                 u8 addr;
 242                 u8 index;
 243         } custom_cmd[150];
 244         u8 res[33];
 245         u8 som_info;
 246         u8 ddr_size;
 247         u8 crc;
 248 } __attribute__ ((__packed__));
 249
 250 #define DART6UL_INFO_STORAGE_GET(n) ((n) & 0x3)
 251 #define DART6UL_INFO_WIFI_GET(n)    ((n) >> 2 & 0x1)
 252 #define DART6UL_INFO_REV_GET(n)     ((n) >> 3 & 0x3)
 253 #define DART6UL_DDRSIZE_IN_MIB(n)   ((n) << 8)
 254 #define DART6UL_INFO_MAGIC          0x32524156
 255
 256 static const char *som_info_storage_to_str(u8 som_info)
 257 {
 258         switch (DART6UL_INFO_STORAGE_GET(som_info)) {
 259         case 0x0: return "none (SD only)";
 260         case 0x1: return "NAND";
 261         case 0x2: return "eMMC";
 262         default: return "unknown";
 263         }
 264 }
 265
 266 static const char *som_info_rev_to_str(u8 som_info)
 267 {
 268         switch (DART6UL_INFO_REV_GET(som_info)) {
 269         case 0x0: return "2.4G";
 270         case 0x1: return "5G";
 271         default: return "unknown";
 272         }
 273 }
 274
 275 int checkboard(void)
 276 {
 277         const char *path = "eeprom0";
 278         struct dart6ul_info *info;
 279         struct udevice *dev;
 280         int ret, off;
 281
 282         off = fdt_path_offset(gd->fdt_blob, path);
 283         if (off < 0) {
 284                 printf("%s: fdt_path_offset() failed: %d\n", __func__, off);
 285                 return off;
 286         }
 287
 288         ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
 289         if (ret) {
 290                 printf("%s: uclass_get_device_by_of_offset() failed: %d\n", __func__, ret);
 291                 return ret;
 292         }
 293
 294         info = malloc(sizeof(struct dart6ul_info));
 295         if (!info)
 296                 return -ENOMEM;
 297
 298         ret = i2c_eeprom_read(dev, 0, (uint8_t *)info,
 299                               sizeof(struct dart6ul_info));
 300         if (ret) {
 301                 printf("%s: i2c_eeprom_read() failed: %d\n", __func__, ret);
 302                 free(info);
 303                 return ret;
 304         }
 305
 306         if (info->magic != DART6UL_INFO_MAGIC) {
 307                 printf("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n",
 308                        info->magic, DART6UL_INFO_MAGIC);
 309                 /* do not fail if the content is invalid */
 310                 free(info);
 311                 return 0;
 312         }
 313
 314         /* make sure strings are null terminated */
 315         info->partnumber[DART6UL_PN_LEN - 1] = '\0';
 316         info->assy[DART6UL_ASSY_LEN - 1] = '\0';
 317         info->date[DART6UL_DATE_LEN - 1] = '\0';
 318
 319         printf("Board: PN: %s, Assy: %s, Date: %s\n"
 320                "       Storage: %s, Wifi: %s, DDR: %d MiB, Rev: %s\n",
 321                info->partnumber,
 322                info->assy,
 323                info->date,
 324                som_info_storage_to_str(info->som_info),
 325                DART6UL_INFO_WIFI_GET(info->som_info) ? "yes" : "no",
 326                DART6UL_DDRSIZE_IN_MIB(info->ddr_size),
 327                som_info_rev_to_str(info->som_info));
 328
 329         free(info);
 330
 331         return 0;
 332 }