Merge branch 'master' of git://www.denx.de/git/u-boot-imx
[platform/kernel/u-boot.git] / board / udoo / udoo_spl.c
1 /*
2  * Copyright (C) 2015 Udoo
3  * Author: Tungyi Lin <tungyilin1127@gmail.com>
4  *         Richard Hu <hakahu@gmail.com>
5  * Based on board/wandboard/spl.c
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/errno.h>
14 #include <asm/gpio.h>
15 #include <asm/imx-common/iomux-v3.h>
16 #include <asm/imx-common/video.h>
17 #include <mmc.h>
18 #include <fsl_esdhc.h>
19 #include <asm/arch/crm_regs.h>
20 #include <asm/io.h>
21 #include <asm/arch/sys_proto.h>
22 #include <spl.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 #if defined(CONFIG_SPL_BUILD)
27 #include <asm/arch/mx6-ddr.h>
28
29 /*
30  * Driving strength:
31  *   0x30 == 40 Ohm
32  *   0x28 == 48 Ohm
33  */
34 #define IMX6DQ_DRIVE_STRENGTH           0x30
35 #define IMX6SDL_DRIVE_STRENGTH  0x28
36
37 /* configure MX6Q/DUAL mmdc DDR io registers */
38 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
39         .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
40         .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
41         .dram_cas = IMX6DQ_DRIVE_STRENGTH,
42         .dram_ras = IMX6DQ_DRIVE_STRENGTH,
43         .dram_reset = IMX6DQ_DRIVE_STRENGTH,
44         .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
45         .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
46         .dram_sdba2 = 0x00000000,
47         .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
48         .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
49         .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
50         .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
51         .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
52         .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
53         .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
54         .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
55         .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
56         .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
57         .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
58         .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
59         .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
60         .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
61         .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
62         .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
63         .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
64         .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
65 };
66
67 /* configure MX6Q/DUAL mmdc GRP io registers */
68 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
69         .grp_ddr_type = 0x000c0000,
70         .grp_ddrmode_ctl = 0x00020000,
71         .grp_ddrpke = 0x00000000,
72         .grp_addds = IMX6DQ_DRIVE_STRENGTH,
73         .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
74         .grp_ddrmode = 0x00020000,
75         .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
76         .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
77         .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
78         .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
79         .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
80         .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
81         .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
82         .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
83 };
84
85 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
86 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
87         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
88         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
89         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
90         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
91         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
92         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
93         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
94         .dram_sdba2 = 0x00000000,
95         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
96         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
97         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
98         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
99         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
100         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
101         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
102         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
103         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
104         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
105         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
106         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
107         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
108         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
109         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
110         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
111         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
112         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
113 };
114
115 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
116 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
117         .grp_ddr_type = 0x000c0000,
118         .grp_ddrmode_ctl = 0x00020000,
119         .grp_ddrpke = 0x00000000,
120         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
121         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
122         .grp_ddrmode = 0x00020000,
123         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
124         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
125         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
126         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
127         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
128         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
129         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
130         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
131 };
132
133 /* MT41K128M16JT-125 */
134 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
135         /* quad = 1066, duallite = 800 */
136         .mem_speed = 1066,
137         .density = 2,
138         .width = 16,
139         .banks = 8,
140         .rowaddr = 14,
141         .coladdr = 10,
142         .pagesz = 2,
143         .trcd = 1375,
144         .trcmin = 4875,
145         .trasmin = 3500,
146         .SRT = 0,
147 };
148
149 static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
150         .p0_mpwldectrl0 = 0x00350035,
151         .p0_mpwldectrl1 = 0x001F001F,
152         .p1_mpwldectrl0 = 0x00010001,
153         .p1_mpwldectrl1 = 0x00010001,
154         .p0_mpdgctrl0 = 0x43510360,
155         .p0_mpdgctrl1 = 0x0342033F,
156         .p1_mpdgctrl0 = 0x033F033F,
157         .p1_mpdgctrl1 = 0x03290266,
158         .p0_mprddlctl = 0x4B3E4141,
159         .p1_mprddlctl = 0x47413B4A,
160         .p0_mpwrdlctl = 0x42404843,
161         .p1_mpwrdlctl = 0x4C3F4C45,
162 };
163
164 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
165         .p0_mpwldectrl0 = 0x002F0038,
166         .p0_mpwldectrl1 = 0x001F001F,
167         .p1_mpwldectrl0 = 0x001F001F,
168         .p1_mpwldectrl1 = 0x001F001F,
169         .p0_mpdgctrl0 = 0x425C0251,
170         .p0_mpdgctrl1 = 0x021B021E,
171         .p1_mpdgctrl0 = 0x021B021E,
172         .p1_mpdgctrl1 = 0x01730200,
173         .p0_mprddlctl = 0x45474C45,
174         .p1_mprddlctl = 0x44464744,
175         .p0_mpwrdlctl = 0x3F3F3336,
176         .p1_mpwrdlctl = 0x32383630,
177 };
178
179 /* DDR 64bit 1GB */
180 static struct mx6_ddr_sysinfo mem_qdl = {
181         .dsize = 2,
182         .cs1_mirror = 0,
183         /* config for full 4GB range so that get_mem_size() works */
184         .cs_density = 32,
185         .ncs = 1,
186         .bi_on = 1,
187         /* quad = 2, duallite = 1 */
188         .rtt_nom = 2,
189         /* quad = 2, duallite = 1 */
190         .rtt_wr = 2,
191         .ralat = 5,
192         .walat = 0,
193         .mif3_mode = 3,
194         .rst_to_cke = 0x23,
195         .sde_to_rst = 0x10,
196 };
197
198 static void ccgr_init(void)
199 {
200         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
201
202         /* set the default clock gate to save power */
203         writel(0x00C03F3F, &ccm->CCGR0);
204         writel(0x0030FC03, &ccm->CCGR1);
205         writel(0x0FFFC000, &ccm->CCGR2);
206         writel(0x3FF00000, &ccm->CCGR3);
207         writel(0x00FFF300, &ccm->CCGR4);
208         writel(0x0F0000C3, &ccm->CCGR5);
209         writel(0x000003FF, &ccm->CCGR6);
210 }
211
212 static void gpr_init(void)
213 {
214         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
215
216         /* enable AXI cache for VDOA/VPU/IPU */
217         writel(0xF00000FF, &iomux->gpr[4]);
218         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
219         writel(0x007F007F, &iomux->gpr[6]);
220         writel(0x007F007F, &iomux->gpr[7]);
221 }
222
223 static void spl_dram_init(void)
224 {
225         if (is_cpu_type(MXC_CPU_MX6DL)) {
226                 mt41k128m16jt_125.mem_speed = 800;
227                 mem_qdl.rtt_nom = 1;
228                 mem_qdl.rtt_wr = 1;
229
230                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
231                 mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
232         } else if (is_cpu_type(MXC_CPU_MX6Q)) {
233                 mt41k128m16jt_125.mem_speed = 1066;
234                 mem_qdl.rtt_nom = 2;
235                 mem_qdl.rtt_wr = 2;
236
237                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
238                 mx6_dram_cfg(&mem_qdl, &mx6q_1g_mmdc_calib, &mt41k128m16jt_125);
239         }
240
241         udelay(100);
242 }
243
244 void board_init_f(ulong dummy)
245 {
246         ccgr_init();
247
248         /* setup AIPS and disable watchdog */
249         arch_cpu_init();
250
251         gpr_init();
252
253         /* iomux */
254         board_early_init_f();
255
256         /* setup GP timer */
257         timer_init();
258
259         /* UART clocks enabled and gd valid - init serial console */
260         preloader_console_init();
261
262         /* DDR initialization */
263         spl_dram_init();
264
265         /* Clear the BSS. */
266         memset(__bss_start, 0, __bss_end - __bss_start);
267
268         /* load/boot image from boot device */
269         board_init_r(NULL, 0);
270 }
271 #endif