board/udoo/neo/neo.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
   4  * Copyright (C) Jasbir Matharu
   5  * Copyright (C) UDOO Team
   6  *
   7  * Author: Breno Lima <breno.lima@nxp.com>
   8  * Author: Francesco Montefoschi <francesco.monte@gmail.com>
   9  */
  10
  11 #include <init.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/iomux.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <asm/global_data.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <dm.h>
  21 #include <env.h>
  22 #include <mmc.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/mach-imx/mxc_i2c.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <spl.h>
  29 #include <linux/delay.h>
  30 #include <linux/sizes.h>
  31 #include <common.h>
  32 #include <i2c.h>
  33 #include <power/pmic.h>
  34 #include <power/pfuze3000_pmic.h>
  35 #include <malloc.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 enum {
  40         UDOO_NEO_TYPE_BASIC,
  41         UDOO_NEO_TYPE_BASIC_KS,
  42         UDOO_NEO_TYPE_FULL,
  43         UDOO_NEO_TYPE_EXTENDED,
  44 };
  45
  46 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  47         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  48         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  49
  50 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  51         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  52         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  53
  54 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |               \
  55         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  56         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |               \
  57         PAD_CTL_ODE)
  58
  59 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  60         PAD_CTL_SPEED_MED   |                                   \
  61         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  62
  63 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
  64         PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
  65
  66 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
  67         PAD_CTL_SPEED_MED   | PAD_CTL_SRE_FAST)
  68
  69 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED |  \
  70         PAD_CTL_DSE_40ohm)
  71
  72 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |              \
  73         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  74         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  75 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) |     \
  76         MUX_MODE_SION)
  77
  78 #define OCRAM_START     0x8f8000
  79
  80 int dram_init(void)
  81 {
  82         gd->ram_size = imx_ddr_size();
  83         return 0;
  84 }
  85
  86 #ifdef CONFIG_SYS_I2C_MXC
  87 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  88 /* I2C1 for PMIC */
  89 static struct i2c_pads_info i2c_pad_info1 = {
  90         .scl = {
  91                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
  92                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
  93                 .gp = IMX_GPIO_NR(1, 0),
  94         },
  95         .sda = {
  96                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
  97                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
  98                 .gp = IMX_GPIO_NR(1, 1),
  99         },
 100 };
 101 #endif
 102
 103 #if CONFIG_IS_ENABLED(POWER_LEGACY)
 104 int power_init_board(void)
 105 {
 106         struct pmic *p;
 107         int ret;
 108         unsigned int reg, rev_id;
 109
 110         ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
 111         if (ret)
 112                 return ret;
 113
 114         p = pmic_get("PFUZE3000");
 115         ret = pmic_probe(p);
 116         if (ret)
 117                 return ret;
 118
 119         pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
 120         pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
 121         printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 122
 123         /* disable Low Power Mode during standby mode */
 124         pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
 125         reg |= 0x1;
 126         ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
 127         if (ret)
 128                 return ret;
 129
 130         ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
 131         if (ret)
 132                 return ret;
 133
 134         ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
 135         if (ret)
 136                 return ret;
 137
 138         ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
 139         if (ret)
 140                 return ret;
 141
 142         ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
 143         if (ret)
 144                 return ret;
 145
 146         /* set SW1A standby voltage 0.975V */
 147         pmic_reg_read(p, PFUZE3000_SW1ASTBY, &reg);
 148         reg &= ~0x3f;
 149         reg |= PFUZE3000_SW1AB_SETP(9750);
 150         ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
 151         if (ret)
 152                 return ret;
 153
 154         /* set SW1B standby voltage 0.975V */
 155         pmic_reg_read(p, PFUZE3000_SW1BSTBY, &reg);
 156         reg &= ~0x3f;
 157         reg |= PFUZE3000_SW1AB_SETP(9750);
 158         ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
 159         if (ret)
 160                 return ret;
 161
 162         /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
 163         pmic_reg_read(p, PFUZE3000_SW1ACONF, &reg);
 164         reg &= ~0xc0;
 165         reg |= 0x40;
 166         ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
 167         if (ret)
 168                 return ret;
 169
 170         /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
 171         pmic_reg_read(p, PFUZE3000_SW1BCONF, &reg);
 172         reg &= ~0xc0;
 173         reg |= 0x40;
 174         ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
 175         if (ret)
 176                 return ret;
 177
 178         /* set VDD_ARM_IN to 1.350V */
 179         pmic_reg_read(p, PFUZE3000_SW1AVOLT, &reg);
 180         reg &= ~0x3f;
 181         reg |= PFUZE3000_SW1AB_SETP(13500);
 182         ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
 183         if (ret)
 184                 return ret;
 185
 186         /* set VDD_SOC_IN to 1.350V */
 187         pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
 188         reg &= ~0x3f;
 189         reg |= PFUZE3000_SW1AB_SETP(13500);
 190         ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
 191         if (ret)
 192                 return ret;
 193
 194         /* set DDR_1_5V to 1.350V */
 195         pmic_reg_read(p, PFUZE3000_SW3VOLT, &reg);
 196         reg &= ~0x0f;
 197         reg |= PFUZE3000_SW3_SETP(13500);
 198         ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
 199         if (ret)
 200                 return ret;
 201
 202         /* set VGEN2_1V5 to 1.5V */
 203         pmic_reg_read(p, PFUZE3000_VLDO2CTL, &reg);
 204         reg &= ~0x0f;
 205         reg |= PFUZE3000_VLDO_SETP(15000);
 206         /*  enable  */
 207         reg |= 0x10;
 208         ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
 209         if (ret)
 210                 return ret;
 211
 212         return 0;
 213 }
 214 #endif
 215
 216 static iomux_v3_cfg_t const uart1_pads[] = {
 217         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 218         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 219 };
 220
 221 static iomux_v3_cfg_t const usdhc2_pads[] = {
 222         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 223         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 224         MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 225         MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 226         MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 227         MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 228         /* CD pin */
 229         MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
 230         /* Power */
 231         MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
 232 };
 233
 234 static iomux_v3_cfg_t const phy_control_pads[] = {
 235         /* 25MHz Ethernet PHY Clock */
 236         MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
 237         MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 238 };
 239
 240 static iomux_v3_cfg_t const wdog_b_pad = {
 241         MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 242 };
 243
 244 static iomux_v3_cfg_t const peri_3v3_pads[] = {
 245         MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 246 };
 247
 248 static void setup_iomux_uart(void)
 249 {
 250         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 251 }
 252
 253 static int setup_fec(void)
 254 {
 255         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 256         int reg;
 257
 258         imx_iomux_v3_setup_multiple_pads(phy_control_pads,
 259                                          ARRAY_SIZE(phy_control_pads));
 260
 261         /* Reset PHY */
 262         gpio_request(IMX_GPIO_NR(2, 1), "enet_rst");
 263         gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
 264         udelay(10000);
 265         gpio_set_value(IMX_GPIO_NR(2, 1), 1);
 266         udelay(100);
 267
 268         reg = readl(&anatop->pll_enet);
 269         reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
 270         writel(reg, &anatop->pll_enet);
 271
 272         return enable_fec_anatop_clock(0, ENET_25MHZ);
 273 }
 274
 275 int board_init(void)
 276 {
 277         /* Address of boot parameters */
 278         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 279
 280         /*
 281          * Because kernel set WDOG_B mux before pad with the commone pinctrl
 282          * framwork now and wdog reset will be triggered once set WDOG_B mux
 283          * with default pad setting, we set pad setting here to workaround this.
 284          * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
 285          * as GPIO mux firstly here to workaround it.
 286          */
 287         imx_iomux_v3_setup_pad(wdog_b_pad);
 288
 289         /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
 290         imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
 291                                          ARRAY_SIZE(peri_3v3_pads));
 292
 293         /* Active high for ncp692 */
 294         gpio_request(IMX_GPIO_NR(4, 16), "ncp692");
 295         gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
 296
 297 #ifdef CONFIG_SYS_I2C_MXC
 298         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 299 #endif
 300
 301         setup_fec();
 302
 303         return 0;
 304 }
 305
 306 int board_early_init_f(void)
 307 {
 308         setup_iomux_uart();
 309
 310         return 0;
 311 }
 312
 313 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 314         {USDHC2_BASE_ADDR},
 315 };
 316
 317 #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
 318 #define USDHC2_CD_GPIO  IMX_GPIO_NR(6, 2)
 319
 320 int board_mmc_getcd(struct mmc *mmc)
 321 {
 322         return !gpio_get_value(USDHC2_CD_GPIO);
 323 }
 324
 325 int board_mmc_init(struct bd_info *bis)
 326 {
 327         SETUP_IOMUX_PADS(usdhc2_pads);
 328         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 329         usdhc_cfg[0].max_bus_width = 4;
 330         gpio_request(IMX_GPIO_NR(6, 1), "usdhc2_pwr");
 331         gpio_request(IMX_GPIO_NR(6, 2), "usdhc2_cd");
 332         gpio_direction_input(USDHC2_CD_GPIO);
 333         gpio_direction_output(USDHC2_PWR_GPIO, 1);
 334
 335         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 336 }
 337
 338 static char *board_string(int type)
 339 {
 340         switch (type) {
 341         case UDOO_NEO_TYPE_BASIC:
 342                 return "BASIC";
 343         case UDOO_NEO_TYPE_BASIC_KS:
 344                 return "BASICKS";
 345         case UDOO_NEO_TYPE_FULL:
 346                 return "FULL";
 347         case UDOO_NEO_TYPE_EXTENDED:
 348                 return "EXTENDED";
 349         }
 350         return "UNDEFINED";
 351 }
 352
 353 int checkboard(void)
 354 {
 355         int *board_type = (int *)OCRAM_START;
 356
 357         printf("Board: UDOO Neo %s\n", board_string(*board_type));
 358         return 0;
 359 }
 360
 361 int board_late_init(void)
 362 {
 363         int *board_type = (int *)OCRAM_START;
 364
 365 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 366         env_set("board_name", board_string(*board_type));
 367 #endif
 368
 369         return 0;
 370 }
 371
 372 #ifdef CONFIG_SPL_BUILD
 373
 374 #include <linux/libfdt.h>
 375 #include <asm/arch/mx6-ddr.h>
 376
 377 static const iomux_v3_cfg_t board_recognition_pads[] = {
 378         /*Connected to R184*/
 379         MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
 380         /*Connected to R185*/
 381         MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
 382 };
 383
 384 static int get_board_value(void)
 385 {
 386         int r184, r185;
 387
 388         imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
 389                                          ARRAY_SIZE(board_recognition_pads));
 390
 391         gpio_request(IMX_GPIO_NR(4, 13), "r184");
 392         gpio_request(IMX_GPIO_NR(4, 0), "r185");
 393         gpio_direction_input(IMX_GPIO_NR(4, 13));
 394         gpio_direction_input(IMX_GPIO_NR(4, 0));
 395
 396         r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
 397         r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
 398
 399         /*
 400          * Machine selection -
 401          * Machine          r184,    r185
 402          * ---------------------------------
 403          * Basic              0        0
 404          * Basic Ks           0        1
 405          * Full               1        0
 406          * Extended           1        1
 407          */
 408
 409         return (r184 << 1) + r185;
 410 }
 411
 412 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
 413         .dram_dqm0 = 0x00000028,
 414         .dram_dqm1 = 0x00000028,
 415         .dram_dqm2 = 0x00000028,
 416         .dram_dqm3 = 0x00000028,
 417         .dram_ras = 0x00000020,
 418         .dram_cas = 0x00000020,
 419         .dram_odt0 = 0x00000020,
 420         .dram_odt1 = 0x00000020,
 421         .dram_sdba2 = 0x00000000,
 422         .dram_sdcke0 = 0x00003000,
 423         .dram_sdcke1 = 0x00003000,
 424         .dram_sdclk_0 = 0x00000030,
 425         .dram_sdqs0 = 0x00000028,
 426         .dram_sdqs1 = 0x00000028,
 427         .dram_sdqs2 = 0x00000028,
 428         .dram_sdqs3 = 0x00000028,
 429         .dram_reset = 0x00000020,
 430 };
 431
 432 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
 433         .grp_addds = 0x00000020,
 434         .grp_ddrmode_ctl = 0x00020000,
 435         .grp_ddrpke = 0x00000000,
 436         .grp_ddrmode = 0x00020000,
 437         .grp_b0ds = 0x00000028,
 438         .grp_b1ds = 0x00000028,
 439         .grp_ctlds = 0x00000020,
 440         .grp_ddr_type = 0x000c0000,
 441         .grp_b2ds = 0x00000028,
 442         .grp_b3ds = 0x00000028,
 443 };
 444
 445 static const struct mx6_mmdc_calibration neo_mmcd_calib = {
 446         .p0_mpwldectrl0 = 0x000E000B,
 447         .p0_mpwldectrl1 = 0x000E0010,
 448         .p0_mpdgctrl0 = 0x41600158,
 449         .p0_mpdgctrl1 = 0x01500140,
 450         .p0_mprddlctl = 0x3A383E3E,
 451         .p0_mpwrdlctl = 0x3A383C38,
 452 };
 453
 454 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
 455         .p0_mpwldectrl0 = 0x001E0022,
 456         .p0_mpwldectrl1 = 0x001C0019,
 457         .p0_mpdgctrl0 = 0x41540150,
 458         .p0_mpdgctrl1 = 0x01440138,
 459         .p0_mprddlctl = 0x403E4644,
 460         .p0_mpwrdlctl = 0x3C3A4038,
 461 };
 462
 463 /* MT41K256M16 */
 464 static struct mx6_ddr3_cfg neo_mem_ddr = {
 465         .mem_speed = 1600,
 466         .density = 4,
 467         .width = 16,
 468         .banks = 8,
 469         .rowaddr = 15,
 470         .coladdr = 10,
 471         .pagesz = 2,
 472         .trcd = 1375,
 473         .trcmin = 4875,
 474         .trasmin = 3500,
 475 };
 476
 477 /* MT41K128M16 */
 478 static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
 479         .mem_speed = 1600,
 480         .density = 2,
 481         .width = 16,
 482         .banks = 8,
 483         .rowaddr = 14,
 484         .coladdr = 10,
 485         .pagesz = 2,
 486         .trcd = 1375,
 487         .trcmin = 4875,
 488         .trasmin = 3500,
 489 };
 490
 491 static void ccgr_init(void)
 492 {
 493         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 494
 495         writel(0xFFFFFFFF, &ccm->CCGR0);
 496         writel(0xFFFFFFFF, &ccm->CCGR1);
 497         writel(0xFFFFFFFF, &ccm->CCGR2);
 498         writel(0xFFFFFFFF, &ccm->CCGR3);
 499         writel(0xFFFFFFFF, &ccm->CCGR4);
 500         writel(0xFFFFFFFF, &ccm->CCGR5);
 501         writel(0xFFFFFFFF, &ccm->CCGR6);
 502         writel(0xFFFFFFFF, &ccm->CCGR7);
 503 }
 504
 505 static void spl_dram_init(void)
 506 {
 507         int *board_type = (int *)OCRAM_START;
 508
 509         struct mx6_ddr_sysinfo sysinfo = {
 510                 .dsize = 1, /* width of data bus: 1 = 32 bits */
 511                 .cs_density = 24,
 512                 .ncs = 1,
 513                 .cs1_mirror = 0,
 514                 .rtt_wr = 2,
 515                 .rtt_nom = 2,           /* RTT_Nom = RZQ/2 */
 516                 .walat = 1,             /* Write additional latency */
 517                 .ralat = 5,             /* Read additional latency */
 518                 .mif3_mode = 3,         /* Command prediction working mode */
 519                 .bi_on = 1,             /* Bank interleaving enabled */
 520                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 521                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 522         };
 523
 524         *board_type = get_board_value();
 525
 526         mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 527         if (*board_type == UDOO_NEO_TYPE_BASIC ||
 528             *board_type == UDOO_NEO_TYPE_BASIC_KS)
 529                 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
 530                              &neo_basic_mem_ddr);
 531         else
 532                 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
 533 }
 534
 535 void board_init_f(ulong dummy)
 536 {
 537         ccgr_init();
 538
 539         /* setup AIPS and disable watchdog */
 540         arch_cpu_init();
 541
 542         board_early_init_f();
 543
 544         /* setup GP timer */
 545         timer_init();
 546
 547         /* UART clocks enabled and gd valid - init serial console */
 548         preloader_console_init();
 549
 550         /* DDR initialization */
 551         spl_dram_init();
 552
 553         /* Clear the BSS. */
 554         memset(__bss_start, 0, __bss_end - __bss_start);
 555
 556         /* load/boot image from boot device */
 557         board_init_r(NULL, 0);
 558 }
 559
 560 #endif