board/udoo/neo/neo.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
   4  * Copyright (C) Jasbir Matharu
   5  * Copyright (C) UDOO Team
   6  *
   7  * Author: Breno Lima <breno.lima@nxp.com>
   8  * Author: Francesco Montefoschi <francesco.monte@gmail.com>
   9  */
  10
  11 #include <init.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/iomux.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <asm/global_data.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <dm.h>
  21 #include <env.h>
  22 #include <mmc.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/mach-imx/mxc_i2c.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <spl.h>
  29 #include <linux/delay.h>
  30 #include <linux/sizes.h>
  31 #include <common.h>
  32 #include <i2c.h>
  33 #include <power/pmic.h>
  34 #include <power/pfuze3000_pmic.h>
  35 #include <malloc.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 enum {
  40         UDOO_NEO_TYPE_BASIC,
  41         UDOO_NEO_TYPE_BASIC_KS,
  42         UDOO_NEO_TYPE_FULL,
  43         UDOO_NEO_TYPE_EXTENDED,
  44 };
  45
  46 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  47         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  48         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  49
  50 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  51         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  52         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  53
  54 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |               \
  55         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  56         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |               \
  57         PAD_CTL_ODE)
  58
  59 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  60         PAD_CTL_SPEED_MED   |                                   \
  61         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  62
  63 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
  64         PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
  65
  66 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
  67         PAD_CTL_SPEED_MED   | PAD_CTL_SRE_FAST)
  68
  69 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED |  \
  70         PAD_CTL_DSE_40ohm)
  71
  72 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |              \
  73         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  74         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  75 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) |     \
  76         MUX_MODE_SION)
  77
  78 int dram_init(void)
  79 {
  80         gd->ram_size = imx_ddr_size();
  81         return 0;
  82 }
  83
  84 #ifdef CONFIG_SYS_I2C_MXC
  85 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  86 /* I2C1 for PMIC */
  87 static struct i2c_pads_info i2c_pad_info1 = {
  88         .scl = {
  89                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
  90                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
  91                 .gp = IMX_GPIO_NR(1, 0),
  92         },
  93         .sda = {
  94                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
  95                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
  96                 .gp = IMX_GPIO_NR(1, 1),
  97         },
  98 };
  99 #endif
 100
 101 #if CONFIG_IS_ENABLED(POWER_LEGACY)
 102 int power_init_board(void)
 103 {
 104         struct pmic *p;
 105         int ret;
 106         unsigned int reg, rev_id;
 107
 108         ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
 109         if (ret)
 110                 return ret;
 111
 112         p = pmic_get("PFUZE3000");
 113         ret = pmic_probe(p);
 114         if (ret)
 115                 return ret;
 116
 117         pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
 118         pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
 119         printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 120
 121         /* disable Low Power Mode during standby mode */
 122         pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
 123         reg |= 0x1;
 124         ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
 125         if (ret)
 126                 return ret;
 127
 128         ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
 129         if (ret)
 130                 return ret;
 131
 132         ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
 133         if (ret)
 134                 return ret;
 135
 136         ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
 137         if (ret)
 138                 return ret;
 139
 140         ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
 141         if (ret)
 142                 return ret;
 143
 144         /* set SW1A standby voltage 0.975V */
 145         pmic_reg_read(p, PFUZE3000_SW1ASTBY, &reg);
 146         reg &= ~0x3f;
 147         reg |= PFUZE3000_SW1AB_SETP(9750);
 148         ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
 149         if (ret)
 150                 return ret;
 151
 152         /* set SW1B standby voltage 0.975V */
 153         pmic_reg_read(p, PFUZE3000_SW1BSTBY, &reg);
 154         reg &= ~0x3f;
 155         reg |= PFUZE3000_SW1AB_SETP(9750);
 156         ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
 157         if (ret)
 158                 return ret;
 159
 160         /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
 161         pmic_reg_read(p, PFUZE3000_SW1ACONF, &reg);
 162         reg &= ~0xc0;
 163         reg |= 0x40;
 164         ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
 165         if (ret)
 166                 return ret;
 167
 168         /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
 169         pmic_reg_read(p, PFUZE3000_SW1BCONF, &reg);
 170         reg &= ~0xc0;
 171         reg |= 0x40;
 172         ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
 173         if (ret)
 174                 return ret;
 175
 176         /* set VDD_ARM_IN to 1.350V */
 177         pmic_reg_read(p, PFUZE3000_SW1AVOLT, &reg);
 178         reg &= ~0x3f;
 179         reg |= PFUZE3000_SW1AB_SETP(13500);
 180         ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
 181         if (ret)
 182                 return ret;
 183
 184         /* set VDD_SOC_IN to 1.350V */
 185         pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
 186         reg &= ~0x3f;
 187         reg |= PFUZE3000_SW1AB_SETP(13500);
 188         ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
 189         if (ret)
 190                 return ret;
 191
 192         /* set DDR_1_5V to 1.350V */
 193         pmic_reg_read(p, PFUZE3000_SW3VOLT, &reg);
 194         reg &= ~0x0f;
 195         reg |= PFUZE3000_SW3_SETP(13500);
 196         ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
 197         if (ret)
 198                 return ret;
 199
 200         /* set VGEN2_1V5 to 1.5V */
 201         pmic_reg_read(p, PFUZE3000_VLDO2CTL, &reg);
 202         reg &= ~0x0f;
 203         reg |= PFUZE3000_VLDO_SETP(15000);
 204         /*  enable  */
 205         reg |= 0x10;
 206         ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
 207         if (ret)
 208                 return ret;
 209
 210         return 0;
 211 }
 212 #endif
 213
 214 static iomux_v3_cfg_t const uart1_pads[] = {
 215         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 216         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 217 };
 218
 219 static iomux_v3_cfg_t const usdhc2_pads[] = {
 220         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 221         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 222         MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 223         MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 224         MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 225         MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 226         /* CD pin */
 227         MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
 228         /* Power */
 229         MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
 230 };
 231
 232 static iomux_v3_cfg_t const phy_control_pads[] = {
 233         /* 25MHz Ethernet PHY Clock */
 234         MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
 235         MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 236 };
 237
 238 static iomux_v3_cfg_t const board_recognition_pads[] = {
 239         /*Connected to R184*/
 240         MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
 241         /*Connected to R185*/
 242         MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
 243 };
 244
 245 static iomux_v3_cfg_t const wdog_b_pad = {
 246         MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 247 };
 248
 249 static iomux_v3_cfg_t const peri_3v3_pads[] = {
 250         MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 251 };
 252
 253 static void setup_iomux_uart(void)
 254 {
 255         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 256 }
 257
 258 static int setup_fec(void)
 259 {
 260         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 261         int reg;
 262
 263         imx_iomux_v3_setup_multiple_pads(phy_control_pads,
 264                                          ARRAY_SIZE(phy_control_pads));
 265
 266         /* Reset PHY */
 267         gpio_request(IMX_GPIO_NR(2, 1), "enet_rst");
 268         gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
 269         udelay(10000);
 270         gpio_set_value(IMX_GPIO_NR(2, 1), 1);
 271         udelay(100);
 272
 273         reg = readl(&anatop->pll_enet);
 274         reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
 275         writel(reg, &anatop->pll_enet);
 276
 277         return enable_fec_anatop_clock(0, ENET_25MHZ);
 278 }
 279
 280 int board_init(void)
 281 {
 282         /* Address of boot parameters */
 283         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 284
 285         /*
 286          * Because kernel set WDOG_B mux before pad with the commone pinctrl
 287          * framwork now and wdog reset will be triggered once set WDOG_B mux
 288          * with default pad setting, we set pad setting here to workaround this.
 289          * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
 290          * as GPIO mux firstly here to workaround it.
 291          */
 292         imx_iomux_v3_setup_pad(wdog_b_pad);
 293
 294         /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
 295         imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
 296                                          ARRAY_SIZE(peri_3v3_pads));
 297
 298         /* Active high for ncp692 */
 299         gpio_request(IMX_GPIO_NR(4, 16), "ncp692");
 300         gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
 301
 302 #ifdef CONFIG_SYS_I2C_MXC
 303         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 304 #endif
 305
 306         setup_fec();
 307
 308         return 0;
 309 }
 310
 311 static int get_board_value(void)
 312 {
 313         int r184, r185;
 314
 315         imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
 316                                          ARRAY_SIZE(board_recognition_pads));
 317
 318         gpio_request(IMX_GPIO_NR(4, 13), "r184");
 319         gpio_request(IMX_GPIO_NR(4, 0), "r185");
 320         gpio_direction_input(IMX_GPIO_NR(4, 13));
 321         gpio_direction_input(IMX_GPIO_NR(4, 0));
 322
 323         r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
 324         r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
 325
 326         /*
 327          * Machine selection -
 328          * Machine          r184,    r185
 329          * ---------------------------------
 330          * Basic              0        0
 331          * Basic Ks           0        1
 332          * Full               1        0
 333          * Extended           1        1
 334          */
 335
 336         return (r184 << 1) + r185;
 337 }
 338
 339 int board_early_init_f(void)
 340 {
 341         setup_iomux_uart();
 342
 343         return 0;
 344 }
 345
 346 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 347         {USDHC2_BASE_ADDR},
 348 };
 349
 350 #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
 351 #define USDHC2_CD_GPIO  IMX_GPIO_NR(6, 2)
 352
 353 int board_mmc_getcd(struct mmc *mmc)
 354 {
 355         return !gpio_get_value(USDHC2_CD_GPIO);
 356 }
 357
 358 int board_mmc_init(struct bd_info *bis)
 359 {
 360         SETUP_IOMUX_PADS(usdhc2_pads);
 361         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 362         usdhc_cfg[0].max_bus_width = 4;
 363         gpio_request(IMX_GPIO_NR(6, 1), "usdhc2_pwr");
 364         gpio_request(IMX_GPIO_NR(6, 2), "usdhc2_cd");
 365         gpio_direction_input(USDHC2_CD_GPIO);
 366         gpio_direction_output(USDHC2_PWR_GPIO, 1);
 367
 368         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 369 }
 370
 371 static char *board_string(void)
 372 {
 373         switch (get_board_value()) {
 374         case UDOO_NEO_TYPE_BASIC:
 375                 return "BASIC";
 376         case UDOO_NEO_TYPE_BASIC_KS:
 377                 return "BASICKS";
 378         case UDOO_NEO_TYPE_FULL:
 379                 return "FULL";
 380         case UDOO_NEO_TYPE_EXTENDED:
 381                 return "EXTENDED";
 382         }
 383         return "UNDEFINED";
 384 }
 385
 386 int checkboard(void)
 387 {
 388         printf("Board: UDOO Neo %s\n", board_string());
 389         return 0;
 390 }
 391
 392 int board_late_init(void)
 393 {
 394 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 395         env_set("board_name", board_string());
 396 #endif
 397
 398         return 0;
 399 }
 400
 401 #ifdef CONFIG_SPL_BUILD
 402
 403 #include <linux/libfdt.h>
 404 #include <asm/arch/mx6-ddr.h>
 405
 406 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
 407         .dram_dqm0 = 0x00000028,
 408         .dram_dqm1 = 0x00000028,
 409         .dram_dqm2 = 0x00000028,
 410         .dram_dqm3 = 0x00000028,
 411         .dram_ras = 0x00000020,
 412         .dram_cas = 0x00000020,
 413         .dram_odt0 = 0x00000020,
 414         .dram_odt1 = 0x00000020,
 415         .dram_sdba2 = 0x00000000,
 416         .dram_sdcke0 = 0x00003000,
 417         .dram_sdcke1 = 0x00003000,
 418         .dram_sdclk_0 = 0x00000030,
 419         .dram_sdqs0 = 0x00000028,
 420         .dram_sdqs1 = 0x00000028,
 421         .dram_sdqs2 = 0x00000028,
 422         .dram_sdqs3 = 0x00000028,
 423         .dram_reset = 0x00000020,
 424 };
 425
 426 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
 427         .grp_addds = 0x00000020,
 428         .grp_ddrmode_ctl = 0x00020000,
 429         .grp_ddrpke = 0x00000000,
 430         .grp_ddrmode = 0x00020000,
 431         .grp_b0ds = 0x00000028,
 432         .grp_b1ds = 0x00000028,
 433         .grp_ctlds = 0x00000020,
 434         .grp_ddr_type = 0x000c0000,
 435         .grp_b2ds = 0x00000028,
 436         .grp_b3ds = 0x00000028,
 437 };
 438
 439 static const struct mx6_mmdc_calibration neo_mmcd_calib = {
 440         .p0_mpwldectrl0 = 0x000E000B,
 441         .p0_mpwldectrl1 = 0x000E0010,
 442         .p0_mpdgctrl0 = 0x41600158,
 443         .p0_mpdgctrl1 = 0x01500140,
 444         .p0_mprddlctl = 0x3A383E3E,
 445         .p0_mpwrdlctl = 0x3A383C38,
 446 };
 447
 448 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
 449         .p0_mpwldectrl0 = 0x001E0022,
 450         .p0_mpwldectrl1 = 0x001C0019,
 451         .p0_mpdgctrl0 = 0x41540150,
 452         .p0_mpdgctrl1 = 0x01440138,
 453         .p0_mprddlctl = 0x403E4644,
 454         .p0_mpwrdlctl = 0x3C3A4038,
 455 };
 456
 457 /* MT41K256M16 */
 458 static struct mx6_ddr3_cfg neo_mem_ddr = {
 459         .mem_speed = 1600,
 460         .density = 4,
 461         .width = 16,
 462         .banks = 8,
 463         .rowaddr = 15,
 464         .coladdr = 10,
 465         .pagesz = 2,
 466         .trcd = 1375,
 467         .trcmin = 4875,
 468         .trasmin = 3500,
 469 };
 470
 471 /* MT41K128M16 */
 472 static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
 473         .mem_speed = 1600,
 474         .density = 2,
 475         .width = 16,
 476         .banks = 8,
 477         .rowaddr = 14,
 478         .coladdr = 10,
 479         .pagesz = 2,
 480         .trcd = 1375,
 481         .trcmin = 4875,
 482         .trasmin = 3500,
 483 };
 484
 485 static void ccgr_init(void)
 486 {
 487         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 488
 489         writel(0xFFFFFFFF, &ccm->CCGR0);
 490         writel(0xFFFFFFFF, &ccm->CCGR1);
 491         writel(0xFFFFFFFF, &ccm->CCGR2);
 492         writel(0xFFFFFFFF, &ccm->CCGR3);
 493         writel(0xFFFFFFFF, &ccm->CCGR4);
 494         writel(0xFFFFFFFF, &ccm->CCGR5);
 495         writel(0xFFFFFFFF, &ccm->CCGR6);
 496         writel(0xFFFFFFFF, &ccm->CCGR7);
 497 }
 498
 499 static void spl_dram_init(void)
 500 {
 501         int board = get_board_value();
 502
 503         struct mx6_ddr_sysinfo sysinfo = {
 504                 .dsize = 1, /* width of data bus: 1 = 32 bits */
 505                 .cs_density = 24,
 506                 .ncs = 1,
 507                 .cs1_mirror = 0,
 508                 .rtt_wr = 2,
 509                 .rtt_nom = 2,           /* RTT_Nom = RZQ/2 */
 510                 .walat = 1,             /* Write additional latency */
 511                 .ralat = 5,             /* Read additional latency */
 512                 .mif3_mode = 3,         /* Command prediction working mode */
 513                 .bi_on = 1,             /* Bank interleaving enabled */
 514                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 515                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 516         };
 517
 518         mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 519         if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
 520                 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
 521                              &neo_basic_mem_ddr);
 522         else
 523                 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
 524 }
 525
 526 void board_init_f(ulong dummy)
 527 {
 528         ccgr_init();
 529
 530         /* setup AIPS and disable watchdog */
 531         arch_cpu_init();
 532
 533         board_early_init_f();
 534
 535         /* setup GP timer */
 536         timer_init();
 537
 538         /* UART clocks enabled and gd valid - init serial console */
 539         preloader_console_init();
 540
 541         /* DDR initialization */
 542         spl_dram_init();
 543
 544         /* Clear the BSS. */
 545         memset(__bss_start, 0, __bss_end - __bss_start);
 546
 547         /* load/boot image from boot device */
 548         board_init_r(NULL, 0);
 549 }
 550
 551 #endif