3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/imx-regs.h>
29 #include <asm/arch/mx5x_pins.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/clock.h>
32 #include <asm/arch/iomux.h>
34 #include <asm/arch/sys_proto.h>
38 #include <fsl_esdhc.h>
43 #include <ipu_pixfmt.h>
45 DECLARE_GLOBAL_DATA_PTR;
47 static struct fb_videomode nec_nl6448bc26_09c = {
52 37650, /* pixclock = 26.56Mhz */
54 16, /* right margin */
55 31, /* upper margin */
56 12, /* lower margin */
60 FB_VMODE_NONINTERLACED, /* vmode */
64 #ifdef CONFIG_HW_WATCHDOG
66 void hw_watchdog_reset(void)
70 /* toggle watchdog trigger pin */
71 val = gpio_get_value(66);
73 gpio_set_value(66, val);
77 static void init_drive_strength(void)
79 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
80 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
81 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
82 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
83 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
84 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
85 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
86 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
87 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
88 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
89 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
90 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
91 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
92 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
93 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
94 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
95 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
96 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
97 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
98 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
99 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
100 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
101 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
102 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
103 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
104 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
105 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
107 /* Setting pad options */
108 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
109 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
110 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
111 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
112 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
113 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
114 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
115 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
116 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
117 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
118 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
119 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
120 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
121 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
122 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
123 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
124 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
125 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
126 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
127 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
128 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
129 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
130 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
131 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
132 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
133 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
134 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
135 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
136 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
137 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
138 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
139 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
140 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
141 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
142 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
143 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
144 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
145 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
146 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
147 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
148 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
149 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
154 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
160 static void setup_weim(void)
162 struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
164 pweim->cs0gcr1 = 0x004100b9;
165 pweim->cs0gcr2 = 0x00000001;
166 pweim->cs0rcr1 = 0x0a018000;
168 pweim->cs0wcr1 = 0x0704a240;
171 static void setup_uart(void)
173 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
174 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
175 /* console RX on Pin EIM_D25 */
176 mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
177 mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
178 /* console TX on Pin EIM_D26 */
179 mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
180 mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
183 #ifdef CONFIG_MXC_SPI
184 void spi_io_init(void)
186 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
187 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
188 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
189 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
191 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
192 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
193 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
194 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
196 /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
197 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
198 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
199 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
200 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
203 * SS1 will be used as GPIO because of uninterrupted
204 * long SPI transmissions (GPIO4_25)
206 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
207 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
208 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
209 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
211 /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
212 mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
213 mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
214 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
215 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
217 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
218 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
219 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
220 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
223 static void reset_peripherals(int reset)
227 /* reset_n is on NANDF_D15 */
228 gpio_direction_output(89, 0);
230 #ifdef CONFIG_VISION2_HW_1_0
232 * set FEC Configuration lines
233 * set levels of FEC config lines
235 gpio_direction_output(75, 0);
236 gpio_direction_output(74, 1);
237 gpio_direction_output(95, 1);
239 /* set direction of FEC config lines */
240 gpio_direction_output(59, 0);
241 gpio_direction_output(60, 0);
242 gpio_direction_output(61, 0);
243 gpio_direction_output(55, 1);
245 /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
246 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
247 /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
248 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
249 /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
250 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
251 /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
252 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
253 /* FEC_COL - sel GPIO (3-10) for configuration -> 1 */
254 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
255 /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
256 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
257 /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
258 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
262 * activate reset_n pin
263 * Select mux mode: ALT3 mux port: NAND D15
265 mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
266 mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
267 PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
269 /* set FEC Control lines */
270 gpio_direction_input(89);
273 #ifdef CONFIG_VISION2_HW_1_0
275 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
276 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
279 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
280 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
283 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
284 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
287 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
288 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
291 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
292 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
295 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
296 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
299 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
300 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
305 static void power_init_mx51(void)
313 /* Write needed to Power Gate 2 register */
314 pmic_reg_read(p, REG_POWER_MISC, &val);
316 /* enable VCAM with 2.775V to enable read from PMIC */
317 val = VCAMCONFIG | VCAMEN;
318 pmic_reg_write(p, REG_MODE_1, val);
321 * Set switchers in Auto in NORMAL mode & STANDBY mode
322 * Setup the switcher mode for SW1 & SW2
324 pmic_reg_read(p, REG_SW_4, &val);
325 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
326 (SWMODE_MASK << SWMODE2_SHIFT)));
327 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
328 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
329 pmic_reg_write(p, REG_SW_4, val);
331 /* Setup the switcher mode for SW3 & SW4 */
332 pmic_reg_read(p, REG_SW_5, &val);
333 val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
334 (SWMODE_MASK << SWMODE3_SHIFT));
335 val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
336 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
337 pmic_reg_write(p, REG_SW_5, val);
340 /* Set VGEN3 to 1.8V, VCAM to 3.0V */
341 pmic_reg_read(p, REG_SETTING_0, &val);
342 val &= ~(VCAM_MASK | VGEN3_MASK);
344 pmic_reg_write(p, REG_SETTING_0, val);
346 /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
347 pmic_reg_read(p, REG_SETTING_1, &val);
348 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
349 val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
350 pmic_reg_write(p, REG_SETTING_1, val);
352 /* Configure VGEN3 and VCAM regulators to use external PNP */
353 val = VGEN3CONFIG | VCAMCONFIG;
354 pmic_reg_write(p, REG_MODE_1, val);
357 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
358 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
359 VVIDEOEN | VAUDIOEN | VSDEN;
360 pmic_reg_write(p, REG_MODE_1, val);
362 pmic_reg_read(p, REG_POWER_CTL2, &val);
364 pmic_reg_write(p, REG_POWER_CTL2, val);
371 static void setup_gpios(void)
375 /* CAM_SUP_DISn, GPIO1_7 */
376 mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
377 mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
379 /* DAB Display EN, GPIO3_1 */
380 mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
381 mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
383 /* WDOG_TRIGGER, GPIO3_2 */
384 mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
385 mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
387 /* Now we need to trigger the watchdog */
390 /* Display2 TxEN, GPIO3_3 */
391 mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
392 mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
394 /* DAB Light EN, GPIO3_4 */
395 mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
396 mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
398 /* AUDIO_MUTE, GPIO3_5 */
399 mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
400 mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
402 /* SPARE_OUT, GPIO3_6 */
403 mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
404 mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
406 /* BEEPER_EN, GPIO3_26 */
407 mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
408 mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
410 /* POWER_OFF, GPIO3_27 */
411 mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
412 mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
414 /* FRAM_WE, GPIO3_30 */
415 mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
416 mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
418 /* EXPANSION_EN, GPIO4_26 */
419 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
420 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
422 /* PWM Output GPIO1_2 */
423 mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
426 * Set GPIO1_4 to high and output; it is used to reset
427 * the system on reboot
429 gpio_direction_output(4, 1);
431 gpio_direction_output(7, 0);
432 for (i = 65; i < 71; i++)
433 gpio_direction_output(i, 0);
435 gpio_direction_output(94, 0);
437 /* Set POWER_OFF high */
438 gpio_direction_output(91, 1);
440 gpio_direction_output(90, 0);
442 gpio_direction_output(122, 0);
444 gpio_direction_output(121, 1);
449 static void setup_fec(void)
452 mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
453 mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
456 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
457 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
460 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
461 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
464 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
465 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
468 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
469 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
472 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
473 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
476 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
477 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
480 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
481 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
484 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
485 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
488 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
489 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
492 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
493 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
496 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
497 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
500 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
501 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
504 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
505 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
508 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
509 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
512 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
513 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
516 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
517 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
520 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
521 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
524 struct fsl_esdhc_cfg esdhc_cfg[1] = {
525 {MMC_SDHC1_BASE_ADDR},
528 int get_mmc_getcd(u8 *cd, struct mmc *mmc)
530 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
532 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
533 *cd = gpio_get_value(0);
540 #ifdef CONFIG_FSL_ESDHC
541 int board_mmc_init(bd_t *bis)
543 mxc_request_iomux(MX51_PIN_SD1_CMD,
544 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
545 mxc_request_iomux(MX51_PIN_SD1_CLK,
546 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
547 mxc_request_iomux(MX51_PIN_SD1_DATA0,
548 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
549 mxc_request_iomux(MX51_PIN_SD1_DATA1,
550 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
551 mxc_request_iomux(MX51_PIN_SD1_DATA2,
552 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
553 mxc_request_iomux(MX51_PIN_SD1_DATA3,
554 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
555 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
556 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
557 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
559 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
560 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
561 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
562 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
564 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
565 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
566 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
567 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
569 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
570 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
571 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
572 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
574 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
575 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
576 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
577 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
579 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
580 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
581 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
582 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
584 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
585 mxc_request_iomux(MX51_PIN_GPIO1_0,
586 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
587 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
589 mxc_request_iomux(MX51_PIN_GPIO1_1,
590 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
591 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
594 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
595 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
599 void lcd_enable(void)
603 mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
604 mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
606 gpio_set_value(2, 1);
607 mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
609 ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
611 puts("LCD cannot be configured\n");
614 int board_early_init_f(void)
618 init_drive_strength();
620 /* Setup debug led */
621 gpio_direction_output(6, 0);
622 mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
623 mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
625 /* wait a little while to give the pll time to settle */
638 static void backlight(int on)
641 gpio_set_value(65, 1);
643 gpio_set_value(68, 1);
645 gpio_set_value(65, 0);
646 gpio_set_value(68, 0);
652 /* address of boot parameters */
653 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
662 int board_late_init(void)
666 reset_peripherals(1);
668 reset_peripherals(0);
671 /* Early revisions require a second reset */
672 #ifdef CONFIG_VISION2_HW_1_0
673 reset_peripherals(1);
675 reset_peripherals(0);
683 * Do not overwrite the console
684 * Use always serial for U-Boot console
686 int overwrite_console(void)
693 puts("Board: TTControl Vision II CPU V\n");
698 int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
703 return cmd_usage(cmdtp);
705 on = (strcmp(argv[1], "on") == 0);
712 lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,