2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 DECLARE_GLOBAL_DATA_PTR;
36 static long int dram_size (long int, long int *, long int);
38 #define _NOT_USED_ 0xFFFFFFFF
40 const uint sdram_table[] =
43 * Single Read. (Offset 0 in UPMA RAM)
45 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
46 0x1FF5FC47, /* last */
48 * SDRAM Initialization (offset 5 in UPMA RAM)
50 * This is no UPM entry point. The following definition uses
51 * the remaining space to establish an initialization
52 * sequence, which is executed by a RUN command.
55 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
57 * Burst Read. (Offset 8 in UPMA RAM)
59 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
60 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
61 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
62 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
64 * Single Write. (Offset 18 in UPMA RAM)
66 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
67 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
69 * Burst Write. (Offset 20 in UPMA RAM)
71 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
72 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
77 * Refresh (Offset 30 in UPMA RAM)
79 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
80 0xFFFFFC84, 0xFFFFFC07, /* last */
81 _NOT_USED_, _NOT_USED_,
82 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
84 * Exception. (Offset 3c in UPMA RAM)
86 0x7FFFFC07, /* last */
87 _NOT_USED_, _NOT_USED_, _NOT_USED_,
90 /* ------------------------------------------------------------------------- */
94 * Check Board Identity:
96 * Test TQ ID string (TQM8xx...)
97 * If present, check for "L" type (no second DRAM bank),
98 * otherwise "L" type is assumed as default.
100 * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
103 int checkboard (void)
105 char *s = getenv ("serial#");
109 if (!s || strncmp (s, "TQM8", 4)) {
110 puts ("### No HW ID - assuming TQM8xxL\n");
114 if ((*(s + 6) == 'L')) { /* a TQM8xxL type */
115 gd->board_type = 'L';
118 if ((*(s + 6) == 'M')) { /* a TQM8xxM type */
119 gd->board_type = 'M';
122 if ((*(s + 6) == 'D')) { /* a TQM885D type */
123 gd->board_type = 'D';
131 #ifdef CONFIG_VIRTLAB2
132 puts (" (Virtlab2)");
139 /* ------------------------------------------------------------------------- */
141 long int initdram (int board_type)
143 volatile immap_t *immap = (immap_t *) CFG_IMMR;
144 volatile memctl8xx_t *memctl = &immap->im_memctl;
145 long int size8, size9, size10;
146 long int size_b0 = 0;
147 long int size_b1 = 0;
149 upmconfig (UPMA, (uint *) sdram_table,
150 sizeof (sdram_table) / sizeof (uint));
153 * Preliminary prescaler for refresh (depends on number of
154 * banks): This value is selected for four cycles every 62.4 us
155 * with two SDRAM banks or four cycles every 31.2 us with one
156 * bank. It will be adjusted after memory sizing.
158 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
161 * The following value is used as an address (i.e. opcode) for
162 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
163 * the port size is 32bit the SDRAM does NOT "see" the lower two
164 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
167 * | | | | +- Burst Length = 4
168 * | | | +----- Burst Type = Sequential
169 * | | +------- CAS Latency = 2
170 * | +----------- Operating Mode = Standard
171 * +-------------- Write Burst Mode = Programmed Burst Length
173 memctl->memc_mar = 0x00000088;
176 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
177 * preliminary addresses - these have to be modified after the
178 * SDRAM size has been determined.
180 memctl->memc_or2 = CFG_OR2_PRELIM;
181 memctl->memc_br2 = CFG_BR2_PRELIM;
183 #ifndef CONFIG_CAN_DRIVER
184 if ((board_type != 'L') &&
185 (board_type != 'M') &&
186 (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
187 memctl->memc_or3 = CFG_OR3_PRELIM;
188 memctl->memc_br3 = CFG_BR3_PRELIM;
190 #endif /* CONFIG_CAN_DRIVER */
192 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
196 /* perform SDRAM initializsation sequence */
198 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
200 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
203 #ifndef CONFIG_CAN_DRIVER
204 if ((board_type != 'L') &&
205 (board_type != 'M') &&
206 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
207 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
209 memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
212 #endif /* CONFIG_CAN_DRIVER */
214 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
219 * Check Bank 0 Memory Size for re-configuration
223 size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
224 debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
231 size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
232 debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
236 #if defined(CFG_MAMR_10COL)
240 size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
241 debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
244 #endif /* CFG_MAMR_10COL */
246 if ((size8 < size10) && (size9 < size10)) {
248 } else if ((size8 < size9) && (size10 < size9)) {
250 memctl->memc_mamr = CFG_MAMR_9COL;
254 memctl->memc_mamr = CFG_MAMR_8COL;
257 debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
259 #ifndef CONFIG_CAN_DRIVER
260 if ((board_type != 'L') &&
261 (board_type != 'M') &&
262 (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
264 * Check Bank 1 Memory Size
265 * use current column settings
266 * [9 column SDRAM may also be used in 8 column mode,
267 * but then only half the real size will be used.]
269 size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
271 debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
275 #endif /* CONFIG_CAN_DRIVER */
280 * Adjust refresh rate depending on SDRAM type, both banks
281 * For types > 128 MBit leave it at the current (fast) rate
283 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
284 /* reduce to 15.6 us (62.4 us / quad) */
285 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
290 * Final mapping: map bigger bank first
292 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
294 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
295 memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
299 * Position Bank 0 immediately above Bank 1
301 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
302 memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
312 memctl->memc_br2 = 0;
314 /* adjust refresh rate depending on SDRAM type, one bank */
315 reg = memctl->memc_mptpr;
316 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
317 memctl->memc_mptpr = reg;
320 } else { /* SDRAM Bank 0 is bigger - map first */
322 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
324 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
328 * Position Bank 1 immediately above Bank 0
331 ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
333 ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
338 #ifndef CONFIG_CAN_DRIVER
344 memctl->memc_br3 = 0;
345 #endif /* CONFIG_CAN_DRIVER */
347 /* adjust refresh rate depending on SDRAM type, one bank */
348 reg = memctl->memc_mptpr;
349 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
350 memctl->memc_mptpr = reg;
356 #ifdef CONFIG_CAN_DRIVER
357 /* Initialize OR3 / BR3 */
358 memctl->memc_or3 = CFG_OR3_CAN;
359 memctl->memc_br3 = CFG_BR3_CAN;
361 /* Initialize MBMR */
362 memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
364 /* Initialize UPMB for CAN: single read */
365 memctl->memc_mdr = 0xFFFFC004;
366 memctl->memc_mcr = 0x0100 | UPMB;
368 memctl->memc_mdr = 0x0FFFD004;
369 memctl->memc_mcr = 0x0101 | UPMB;
371 memctl->memc_mdr = 0x0FFFC000;
372 memctl->memc_mcr = 0x0102 | UPMB;
374 memctl->memc_mdr = 0x3FFFC004;
375 memctl->memc_mcr = 0x0103 | UPMB;
377 memctl->memc_mdr = 0xFFFFDC05;
378 memctl->memc_mcr = 0x0104 | UPMB;
380 /* Initialize UPMB for CAN: single write */
381 memctl->memc_mdr = 0xFFFCC004;
382 memctl->memc_mcr = 0x0118 | UPMB;
384 memctl->memc_mdr = 0xCFFCD004;
385 memctl->memc_mcr = 0x0119 | UPMB;
387 memctl->memc_mdr = 0x0FFCC000;
388 memctl->memc_mcr = 0x011A | UPMB;
390 memctl->memc_mdr = 0x7FFCC004;
391 memctl->memc_mcr = 0x011B | UPMB;
393 memctl->memc_mdr = 0xFFFDCC05;
394 memctl->memc_mcr = 0x011C | UPMB;
395 #endif /* CONFIG_CAN_DRIVER */
397 #ifdef CONFIG_ISP1362_USB
398 /* Initialize OR5 / BR5 */
399 memctl->memc_or5 = CFG_OR5_ISP1362;
400 memctl->memc_br5 = CFG_BR5_ISP1362;
401 #endif /* CONFIG_ISP1362_USB */
404 return (size_b0 + size_b1);
407 /* ------------------------------------------------------------------------- */
410 * Check memory range for valid RAM. A simple memory test determines
411 * the actually available RAM size between addresses `base' and
412 * `base + maxsize'. Some (not all) hardware errors are detected:
413 * - short between address lines
414 * - short between data lines
417 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
419 volatile immap_t *immap = (immap_t *) CFG_IMMR;
420 volatile memctl8xx_t *memctl = &immap->im_memctl;
422 memctl->memc_mamr = mamr_value;
424 return (get_ram_size(base, maxsize));
427 /* ------------------------------------------------------------------------- */
429 #ifdef CONFIG_PS2MULT
432 #define BASE_BAUD ( 1843200 / 16 )
433 struct serial_state rs_table[] = {
434 { BASE_BAUD, 4, (void*)0xec140000 },
435 { BASE_BAUD, 2, (void*)0xec150000 },
436 { BASE_BAUD, 6, (void*)0xec160000 },
437 { BASE_BAUD, 10, (void*)0xec170000 },
440 #ifdef CONFIG_BOARD_EARLY_INIT_R
441 int board_early_init_r (void)
443 ps2mult_early_init();
447 #endif /* CONFIG_HMI10 */
449 #endif /* CONFIG_PS2MULT */
451 /* ---------------------------------------------------------------------------- */
452 /* HMI10 specific stuff */
453 /* ---------------------------------------------------------------------------- */
456 int misc_init_r (void)
458 # ifdef CONFIG_IDE_LED
459 volatile immap_t *immap = (immap_t *) CFG_IMMR;
461 /* Configure PA15 as output port */
462 immap->im_ioport.iop_padir |= 0x0001;
463 immap->im_ioport.iop_paodr |= 0x0001;
464 immap->im_ioport.iop_papar &= ~0x0001;
465 immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
470 # ifdef CONFIG_IDE_LED
471 void ide_led (uchar led, uchar status)
473 volatile immap_t *immap = (immap_t *) CFG_IMMR;
475 /* We have one led for both pcmcia slots */
476 if (status) { /* led on */
477 immap->im_ioport.iop_padat |= 0x0001;
479 immap->im_ioport.iop_padat &= ~0x0001;
483 #endif /* CONFIG_HMI10 */
485 /* ---------------------------------------------------------------------------- */
486 /* NSCU specific stuff */
487 /* ---------------------------------------------------------------------------- */
490 int misc_init_r (void)
492 volatile immap_t *immr = (immap_t *) CFG_IMMR;
494 /* wake up ethernet module */
495 immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */
496 immr->im_ioport.iop_pcdir |= 0x0004; /* output */
497 immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */
498 immr->im_ioport.iop_pcdat |= 0x0004; /* enable */
502 #endif /* CONFIG_NSCU */
504 /* ------------------------------------------------------------------------- */