2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /* ------------------------------------------------------------------------- */
33 static long int dram_size (long int, long int *, long int);
35 /* ------------------------------------------------------------------------- */
37 #define _NOT_USED_ 0xFFFFFFFF
39 const uint sdram_table[] =
42 * Single Read. (Offset 0 in UPMA RAM)
44 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
45 0x1FF5FC47, /* last */
47 * SDRAM Initialization (offset 5 in UPMA RAM)
49 * This is no UPM entry point. The following definition uses
50 * the remaining space to establish an initialization
51 * sequence, which is executed by a RUN command.
54 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
56 * Burst Read. (Offset 8 in UPMA RAM)
58 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
59 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
60 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
61 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
63 * Single Write. (Offset 18 in UPMA RAM)
65 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
66 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 * Burst Write. (Offset 20 in UPMA RAM)
70 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
71 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
76 * Refresh (Offset 30 in UPMA RAM)
78 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
79 0xFFFFFC84, 0xFFFFFC07, /* last */
80 _NOT_USED_, _NOT_USED_,
81 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
83 * Exception. (Offset 3c in UPMA RAM)
85 0x7FFFFC07, /* last */
86 _NOT_USED_, _NOT_USED_, _NOT_USED_,
89 /* ------------------------------------------------------------------------- */
93 * Check Board Identity:
95 * Test TQ ID string (TQM8xx...)
96 * If present, check for "L" type (no second DRAM bank),
97 * otherwise "L" type is assumed as default.
99 * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
102 int checkboard (void)
104 DECLARE_GLOBAL_DATA_PTR;
106 unsigned char *s = getenv ("serial#");
110 if (!s || strncmp (s, "TQM8", 4)) {
111 puts ("### No HW ID - assuming TQM8xxL\n");
115 if ((*(s + 6) == 'L')) { /* a TQM8xxL type */
116 gd->board_type = 'L';
119 if ((*(s + 6) == 'M')) { /* a TQM8xxM type */
120 gd->board_type = 'M';
133 /* ------------------------------------------------------------------------- */
135 long int initdram (int board_type)
137 volatile immap_t *immap = (immap_t *) CFG_IMMR;
138 volatile memctl8xx_t *memctl = &immap->im_memctl;
139 long int size8, size9;
140 long int size_b0 = 0;
141 long int size_b1 = 0;
143 upmconfig (UPMA, (uint *) sdram_table,
144 sizeof (sdram_table) / sizeof (uint));
147 * Preliminary prescaler for refresh (depends on number of
148 * banks): This value is selected for four cycles every 62.4 us
149 * with two SDRAM banks or four cycles every 31.2 us with one
150 * bank. It will be adjusted after memory sizing.
152 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
155 * The following value is used as an address (i.e. opcode) for
156 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
157 * the port size is 32bit the SDRAM does NOT "see" the lower two
158 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
161 * | | | | +- Burst Length = 4
162 * | | | +----- Burst Type = Sequential
163 * | | +------- CAS Latency = 2
164 * | +----------- Operating Mode = Standard
165 * +-------------- Write Burst Mode = Programmed Burst Length
167 memctl->memc_mar = 0x00000088;
170 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
171 * preliminary addresses - these have to be modified after the
172 * SDRAM size has been determined.
174 memctl->memc_or2 = CFG_OR2_PRELIM;
175 memctl->memc_br2 = CFG_BR2_PRELIM;
177 #ifndef CONFIG_CAN_DRIVER
178 if ((board_type != 'L') &&
179 (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
180 memctl->memc_or3 = CFG_OR3_PRELIM;
181 memctl->memc_br3 = CFG_BR3_PRELIM;
183 #endif /* CONFIG_CAN_DRIVER */
185 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
189 /* perform SDRAM initializsation sequence */
191 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
193 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
196 #ifndef CONFIG_CAN_DRIVER
197 if ((board_type != 'L') &&
198 (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
199 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
201 memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
204 #endif /* CONFIG_CAN_DRIVER */
206 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
211 * Check Bank 0 Memory Size for re-configuration
215 size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
217 debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
224 size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
226 debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
228 if (size8 < size9) { /* leave configuration at 9 columns */
230 } else { /* back to 8 columns */
232 memctl->memc_mamr = CFG_MAMR_8COL;
235 debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
237 #ifndef CONFIG_CAN_DRIVER
238 if ((board_type != 'L') &&
239 (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
241 * Check Bank 1 Memory Size
242 * use current column settings
243 * [9 column SDRAM may also be used in 8 column mode,
244 * but then only half the real size will be used.]
246 size_b1 = dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
248 debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
252 #endif /* CONFIG_CAN_DRIVER */
257 * Adjust refresh rate depending on SDRAM type, both banks
258 * For types > 128 MBit leave it at the current (fast) rate
260 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
261 /* reduce to 15.6 us (62.4 us / quad) */
262 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
267 * Final mapping: map bigger bank first
269 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
271 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
273 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
277 * Position Bank 0 immediately above Bank 1
280 ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
282 ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
292 memctl->memc_br2 = 0;
294 /* adjust refresh rate depending on SDRAM type, one bank */
295 reg = memctl->memc_mptpr;
296 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
297 memctl->memc_mptpr = reg;
300 } else { /* SDRAM Bank 0 is bigger - map first */
302 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
304 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
308 * Position Bank 1 immediately above Bank 0
311 ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
313 ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
318 #ifndef CONFIG_CAN_DRIVER
324 memctl->memc_br3 = 0;
325 #endif /* CONFIG_CAN_DRIVER */
327 /* adjust refresh rate depending on SDRAM type, one bank */
328 reg = memctl->memc_mptpr;
329 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
330 memctl->memc_mptpr = reg;
336 #ifdef CONFIG_CAN_DRIVER
337 /* Initialize OR3 / BR3 */
338 memctl->memc_or3 = CFG_OR3_CAN;
339 memctl->memc_br3 = CFG_BR3_CAN;
341 /* Initialize MBMR */
342 memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
344 /* Initialize UPMB for CAN: single read */
345 memctl->memc_mdr = 0xFFFFC004;
346 memctl->memc_mcr = 0x0100 | UPMB;
348 memctl->memc_mdr = 0x0FFFD004;
349 memctl->memc_mcr = 0x0101 | UPMB;
351 memctl->memc_mdr = 0x0FFFC000;
352 memctl->memc_mcr = 0x0102 | UPMB;
354 memctl->memc_mdr = 0x3FFFC004;
355 memctl->memc_mcr = 0x0103 | UPMB;
357 memctl->memc_mdr = 0xFFFFDC05;
358 memctl->memc_mcr = 0x0104 | UPMB;
360 /* Initialize UPMB for CAN: single write */
361 memctl->memc_mdr = 0xFFFCC004;
362 memctl->memc_mcr = 0x0118 | UPMB;
364 memctl->memc_mdr = 0xCFFCD004;
365 memctl->memc_mcr = 0x0119 | UPMB;
367 memctl->memc_mdr = 0x0FFCC000;
368 memctl->memc_mcr = 0x011A | UPMB;
370 memctl->memc_mdr = 0x7FFCC004;
371 memctl->memc_mcr = 0x011B | UPMB;
373 memctl->memc_mdr = 0xFFFDCC05;
374 memctl->memc_mcr = 0x011C | UPMB;
375 #endif /* CONFIG_CAN_DRIVER */
377 #ifdef CONFIG_ISP1362_USB
378 /* Initialize OR5 / BR5 */
379 memctl->memc_or5 = CFG_OR5_ISP1362;
380 memctl->memc_br5 = CFG_BR5_ISP1362;
381 #endif /* CONFIG_ISP1362_USB */
384 return (size_b0 + size_b1);
387 /* ------------------------------------------------------------------------- */
390 * Check memory range for valid RAM. A simple memory test determines
391 * the actually available RAM size between addresses `base' and
392 * `base + maxsize'. Some (not all) hardware errors are detected:
393 * - short between address lines
394 * - short between data lines
397 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
399 volatile immap_t *immap = (immap_t *) CFG_IMMR;
400 volatile memctl8xx_t *memctl = &immap->im_memctl;
401 volatile long int *addr;
402 ulong cnt, val, size;
403 ulong save[32]; /* to make test non-destructive */
406 memctl->memc_mamr = mamr_value;
408 for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
409 addr = base + cnt; /* pointer arith! */
415 /* write 0 to base address */
420 /* check at base address */
421 if ((val = *addr) != 0) {
422 /* Restore the original data before leaving the function.
425 for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
426 addr = (volatile ulong *) base + cnt;
432 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
433 addr = base + cnt; /* pointer arith! */
439 size = cnt * sizeof (long);
440 /* Restore the original data before returning
442 for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
443 addr = (volatile ulong *) base + cnt;
452 /* ------------------------------------------------------------------------- */