board/tqm85xx/init.S

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * Copyright (C) 2002,2003, Motorola Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <ppc_asm.tmpl>
  26 #include <ppc_defs.h>
  27 #include <asm/cache.h>
  28 #include <asm/mmu.h>
  29 #include <config.h>
  30 #include <mpc85xx.h>
  31
  32
  33 /*
  34  * TLB0 and TLB1 Entries
  35  *
  36  * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
  37  * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
  38  * these TLB entries are established.
  39  *
  40  * The TLB entries for DDR are dynamically setup in spd_sdram()
  41  * and use TLB1 Entries 8 through 15 as needed according to the
  42  * size of DDR memory.
  43  *
  44  * MAS0: tlbsel, esel, nv
  45  * MAS1: valid, iprot, tid, ts, tsize
  46  * MAS2: epn, sharen, x0, x1, w, i, m, g, e
  47  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  48  */
  49
  50 #define entry_start \
  51         mflr    r1      ;       \
  52         bl      0f      ;
  53
  54 #define entry_end \
  55 0:      mflr    r0      ;       \
  56         mtlr    r1      ;       \
  57         blr             ;
  58
  59
  60         .section        .bootpg, "ax"
  61         .globl  tlb1_entry
  62 tlb1_entry:
  63         entry_start
  64
  65         /*
  66          * Number of TLB0 and TLB1 entries in the following table
  67          */
  68         .long 13
  69
  70         /*
  71          * TLB0         16K     Cacheable, non-guarded
  72          * 0xd001_0000  16K     Temporary Global data for initialization
  73          *
  74          * Use four 4K TLB0 entries.  These entries must be cacheable
  75          * as they provide the bootstrap memory before the memory
  76          * controler and real memory have been configured.
  77          *
  78          * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
  79          * and must not collide with other TLB0 entries.
  80          */
  81         .long TLB1_MAS0(0, 0, 0)
  82         .long TLB1_MAS1(1, 0, 0, 0, 0)
  83         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
  84                         0,0,0,0,0,0,0,0)
  85         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
  86                         0,0,0,0,0,1,0,1,0,1)
  87
  88         .long TLB1_MAS0(0, 0, 0)
  89         .long TLB1_MAS1(1, 0, 0, 0, 0)
  90         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
  91                         0,0,0,0,0,0,0,0)
  92         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
  93                         0,0,0,0,0,1,0,1,0,1)
  94
  95         .long TLB1_MAS0(0, 0, 0)
  96         .long TLB1_MAS1(1, 0, 0, 0, 0)
  97         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
  98                         0,0,0,0,0,0,0,0)
  99         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
 100                         0,0,0,0,0,1,0,1,0,1)
 101
 102         .long TLB1_MAS0(0, 0, 0)
 103         .long TLB1_MAS1(1, 0, 0, 0, 0)
 104         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 105                         0,0,0,0,0,0,0,0)
 106         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 107                         0,0,0,0,0,1,0,1,0,1)
 108
 109
 110         /*
 111          * TLB 0, 1:    128M    Non-cacheable, guarded
 112          * 0xf8000000   128M    FLASH
 113          * Out of reset this entry is only 4K.
 114          */
 115         .long TLB1_MAS0(1, 1, 0)
 116         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 117         .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
 118         .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
 119         .long TLB1_MAS0(1, 0, 0)
 120         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 121         .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,1,0,1,0)
 122         .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,0,1,0,1,0,1)
 123
 124         /*
 125          * TLB 2:       256M    Non-cacheable, guarded
 126          * 0x80000000   256M    PCI1 MEM First half
 127          */
 128         .long TLB1_MAS0(1, 2, 0)
 129         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 130         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
 131         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
 132
 133         /*
 134          * TLB 3:       256M    Non-cacheable, guarded
 135          * 0x90000000   256M    PCI1 MEM Second half
 136          */
 137         .long TLB1_MAS0(1, 3, 0)
 138         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 139         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
 140                         0,0,0,0,1,0,1,0)
 141         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
 142                         0,0,0,0,0,1,0,1,0,1)
 143
 144         /*
 145          * TLB 4:       256M    Non-cacheable, guarded
 146          * 0xc0000000   256M    Rapid IO MEM First half
 147          */
 148         .long TLB1_MAS0(1, 4, 0)
 149         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 150         .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
 151         .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
 152
 153         /*
 154          * TLB 5:       256M    Non-cacheable, guarded
 155          * 0xd0000000   256M    Rapid IO MEM Second half
 156          */
 157         .long TLB1_MAS0(1, 5, 0)
 158         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 159         .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
 160                         0,0,0,0,1,0,1,0)
 161         .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
 162                         0,0,0,0,0,1,0,1,0,1)
 163
 164         /*
 165          * TLB 6:       64M     Non-cacheable, guarded
 166          * 0xe000_0000  1M      CCSRBAR
 167          * 0xe200_0000  16M     PCI1 IO
 168          */
 169         .long TLB1_MAS0(1, 6, 0)
 170         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 171         .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
 172         .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
 173
 174         /*
 175          * TLB 7+8:     512M    DDR, cache disabled (needed for memory test)
 176          * 0x00000000  512M     DDR System memory
 177          * Without SPD EEPROM configured DDR, this must be setup manually.
 178          * Make sure the TLB count at the top of this table is correct.
 179          * Likely it needs to be increased by two for these entries.
 180          */
 181         .long TLB1_MAS0(1, 7, 0)
 182         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 183         .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0)
 184         .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
 185         .long TLB1_MAS0(1, 8, 0)
 186         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 187         .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,1,0,1,0)
 188         .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
 189
 190         entry_end
 191
 192 /*
 193  * LAW(Local Access Window) configuration:
 194  *
 195  * 0x0000_0000     0x7fff_ffff     DDR                     2G
 196  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
 197  * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
 198  * 0xe000_0000     0xe000_ffff     CCSR                    1M
 199  * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
 200  * 0xf800_0000     0xf80f_ffff     BCSR                    1M
 201  * 0xfe00_0000     0xffff_ffff     FLASH (boot bank)       32M
 202  *
 203  * Notes:
 204  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
 205  *    If flash is 8M at default position (last 8M), no LAW needed.
 206  */
 207
 208 #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
 209 #define LAWAR0  (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
 210
 211 #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
 212 #define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
 213
 214 #define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
 215 #define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
 216
 217 #define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
 218 #define LAWAR3  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
 219
 220 /*
 221  * Rapid IO at 0xc000_0000 for 512 M
 222  */
 223 #define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
 224 #define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
 225
 226
 227         .section .bootpg, "ax"
 228         .globl  law_entry
 229 law_entry:
 230         entry_start
 231         .long 0x05
 232         .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
 233         .long LAWBAR4,LAWAR4
 234         entry_end