3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/mpc8349_pci.h>
32 #include <asm-ppc/mmu.h>
34 #if defined(CONFIG_PCI)
38 #define IOSYNC asm("eieio")
39 #define ISYNC asm("isync")
40 #define SYNC asm("sync")
41 #define FPW FLASH_PORT_WIDTH
42 #define FPWV FLASH_PORT_WIDTHV
44 #define DDR_MAX_SIZE_PER_CS 0x20000000
46 #if defined(DDR_CASLAT_20)
47 #define TIMING_CASLAT TIMING_CFG1_CASLAT_20
48 #define MODE_CASLAT DDR_MODE_CASLAT_20
50 #define TIMING_CASLAT TIMING_CFG1_CASLAT_25
51 #define MODE_CASLAT DDR_MODE_CASLAT_25
54 #define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
57 /* Global variable used to store detected number of banks */
58 int tqm834x_num_flash_banks;
60 /* External definitions */
61 ulong flash_get_size (ulong base, int banknum);
62 extern flash_info_t flash_info[];
63 extern long spd_sdram (void);
66 static int detect_num_flash_banks(void);
67 static long int get_ddr_bank_size(short cs, volatile long *base);
68 static void set_cs_bounds(short cs, long base, long size);
69 static void set_cs_config(short cs, long config);
70 static void set_ddr_config(void);
73 static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
75 /**************************************************************************
76 * Board initialzation after relocation to RAM. Used to detect the number
77 * of Flash banks on TQM834x.
79 int board_early_init_r (void) {
80 /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
81 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
84 /* detect the number of Flash banks */
85 return detect_num_flash_banks();
88 /**************************************************************************
89 * DRAM initalization and size detection
91 long int initdram (int board_type)
97 /* during size detection, set up the max DDRLAW size */
98 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE;
99 im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
101 /* set CS bounds to maximum size */
102 for(cs = 0; cs < 4; ++cs) {
104 CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
105 DDR_MAX_SIZE_PER_CS);
107 set_cs_config(cs, INITIAL_CS_CONFIG);
110 /* configure ddr controller */
115 /* enable DDR controller */
116 im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
118 SDRAM_CFG_SDRAM_TYPE_DDR);
124 for(cs = 0; cs < 4; ++cs) {
125 debug("\nDetecting Bank%d\n", cs);
127 bank_size = get_ddr_bank_size(cs,
128 (volatile long*)(CFG_DDR_BASE + size));
131 debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
133 /* exit if less than one bank */
134 if(size < DDR_MAX_SIZE_PER_CS) break;
140 /**************************************************************************
143 int checkboard (void)
145 puts("Board: TQM834x\n");
148 printf("PCI1: 32 bit, %d MHz (compiled)\n",
149 CONFIG_SYS_CLK_FREQ / 1000000);
151 printf("PCI1: disabled\n");
157 #if defined(CONFIG_PCI)
159 * Initialize PCI Devices, report devices found
162 /* FIXME: No PCI support */
164 #endif /* CONFIG_PCI */
166 /**************************************************************************
173 extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
175 pci_mpc83xx_init(hose);
176 #endif /* CONFIG_PCI */
179 /**************************************************************************
183 *************************************************************************/
185 /**************************************************************************
186 * Detect the number of flash banks (1 or 2). Store it in
187 * a global variable tqm834x_num_flash_banks.
188 * Bank detection code based on the Monitor code.
190 static int detect_num_flash_banks(void)
192 typedef unsigned long FLASH_PORT_WIDTH;
193 typedef volatile unsigned long FLASH_PORT_WIDTHV;
202 tqm834x_num_flash_banks = 2; /* assume two banks */
204 /* Get bank 1 and 2 information */
205 bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
206 debug("Bank1 size: %lu\n", bank1_size);
207 bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1);
208 debug("Bank2 size: %lu\n", bank2_size);
209 total_size = bank1_size + bank2_size;
211 if (bank2_size > 0) {
212 /* Seems like we've got bank 2, but maybe it's mirrored 1 */
214 /* Set the base addresses */
215 bank1_base = (FPWV *) (CFG_FLASH_BASE);
216 bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size);
218 /* Put bank 2 into CFI command mode and read */
219 bank2_base[0x55] = 0x00980098;
222 bank2_read = bank2_base[0x10];
224 /* Read from bank 1 (it's in read mode) */
225 bank1_read = bank1_base[0x10];
228 bank1_base[0] = 0x00F000F0;
229 bank2_base[0] = 0x00F000F0;
231 if (bank2_read == bank1_read) {
233 * Looks like just one bank, but not sure yet. Let's
234 * read from bank 2 in autosoelect mode.
236 bank2_base[0x0555] = 0x00AA00AA;
237 bank2_base[0x02AA] = 0x00550055;
238 bank2_base[0x0555] = 0x00900090;
241 bank2_read = bank2_base[0x10];
243 /* Read from bank 1 (it's in read mode) */
244 bank1_read = bank1_base[0x10];
247 bank1_base[0] = 0x00F000F0;
248 bank2_base[0] = 0x00F000F0;
250 if (bank2_read == bank1_read) {
252 * In both CFI command and autoselect modes,
253 * we got the some data reading from Flash.
254 * There is only one mirrored bank.
256 tqm834x_num_flash_banks = 1;
257 total_size = bank1_size;
262 debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
264 /* set OR0 and BR0 */
265 im->lbus.bank[0].or = CFG_OR_TIMING_FLASH |
266 (-(total_size) & OR_GPCM_AM);
267 im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) |
268 (BR_MS_GPCM | BR_PS_32 | BR_V);
273 /*************************************************************************
274 * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
276 static long int get_ddr_bank_size(short cs, volatile long *base)
278 /* This array lists all valid DDR SDRAM configurations, with
279 * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
280 * The last entry has to to have size equal 0 and is igonred during
281 * autodection. Bank sizes must be in increasing order of size
288 {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20},
289 {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20},
290 {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20},
291 {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20},
292 {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20},
293 {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20},
294 {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20},
295 {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20},
304 for(i = 0; conf[i].size != 0; ++i) {
306 /* set sdram bank configuration */
307 set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
309 debug("Getting RAM size...\n");
310 size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
312 if((size == conf[i].size) && (i == detected + 1))
315 debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
324 /* disable empty cs */
325 debug("\nNo valid configurations for CS%d, disabling...\n", cs);
326 set_cs_config(cs, 0);
330 debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
331 conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
333 /* configure cs ro detected params */
334 set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
337 set_cs_bounds(cs, (long)base, conf[detected].size);
339 return(conf[detected].size);
342 /**************************************************************************
343 * Sets DDR bank CS bounds.
345 static void set_cs_bounds(short cs, long base, long size)
347 debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs);
349 im->ddr.csbnds[cs].csbnds = 0x00000000;
351 im->ddr.csbnds[cs].csbnds =
352 ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
353 (((base + size - 1) >> CSBNDS_EA_SHIFT) &
359 /**************************************************************************
360 * Sets DDR banks CS configuration.
361 * config == 0x00000000 disables the CS.
363 static void set_cs_config(short cs, long config)
365 debug("Setting config %08x for cs %d\n", config, cs);
366 im->ddr.cs_config[cs] = config;
370 /**************************************************************************
371 * Sets DDR clocks, timings and configuration.
373 static void set_ddr_config(void) {
375 im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
376 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
379 /* timing configuration */
380 im->ddr.timing_cfg_1 =
381 (4 << TIMING_CFG1_PRETOACT_SHIFT) |
382 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
383 (4 << TIMING_CFG1_ACTTORW_SHIFT) |
384 (5 << TIMING_CFG1_REFREC_SHIFT) |
385 (3 << TIMING_CFG1_WRREC_SHIFT) |
386 (3 << TIMING_CFG1_ACTTOACT_SHIFT) |
387 (1 << TIMING_CFG1_WRTORD_SHIFT) |
388 (TIMING_CFG1_CASLAT & TIMING_CASLAT);
390 im->ddr.timing_cfg_2 =
391 TIMING_CFG2_CPO_DEF |
392 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
395 /* don't enable DDR controller yet */
398 SDRAM_CFG_SDRAM_TYPE_DDR;
403 ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
404 SDRAM_MODE_ESD_SHIFT) |
405 ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
406 SDRAM_MODE_SD_SHIFT) |
407 ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
411 /* Set fast SDRAM refresh rate */
412 im->ddr.sdram_interval =
413 (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
414 (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);