3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/mpc8349_pci.h>
32 #include <asm-ppc/mmu.h>
35 #define IOSYNC asm("eieio")
36 #define ISYNC asm("isync")
37 #define SYNC asm("sync")
38 #define FPW FLASH_PORT_WIDTH
39 #define FPWV FLASH_PORT_WIDTHV
41 #define DDR_MAX_SIZE_PER_CS 0x20000000
43 #if defined(DDR_CASLAT_20)
44 #define TIMING_CASLAT TIMING_CFG1_CASLAT_20
45 #define MODE_CASLAT DDR_MODE_CASLAT_20
47 #define TIMING_CASLAT TIMING_CFG1_CASLAT_25
48 #define MODE_CASLAT DDR_MODE_CASLAT_25
51 #define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
54 /* Global variable used to store detected number of banks */
55 int tqm834x_num_flash_banks;
57 /* External definitions */
58 ulong flash_get_size (ulong base, int banknum);
59 extern flash_info_t flash_info[];
60 extern long spd_sdram (void);
63 static int detect_num_flash_banks(void);
64 static long int get_ddr_bank_size(short cs, volatile long *base);
65 static void set_cs_bounds(short cs, long base, long size);
66 static void set_cs_config(short cs, long config);
67 static void set_ddr_config(void);
70 static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
72 /**************************************************************************
73 * Board initialzation after relocation to RAM. Used to detect the number
74 * of Flash banks on TQM834x.
76 int board_early_init_r (void) {
77 /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
78 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
81 /* detect the number of Flash banks */
82 return detect_num_flash_banks();
85 /**************************************************************************
86 * DRAM initalization and size detection
88 long int initdram (int board_type)
94 /* during size detection, set up the max DDRLAW size */
95 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE;
96 im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
98 /* set CS bounds to maximum size */
99 for(cs = 0; cs < 4; ++cs) {
101 CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
102 DDR_MAX_SIZE_PER_CS);
104 set_cs_config(cs, INITIAL_CS_CONFIG);
107 /* configure ddr controller */
112 /* enable DDR controller */
113 im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
115 SDRAM_CFG_SDRAM_TYPE_DDR);
121 for(cs = 0; cs < 4; ++cs) {
122 debug("\nDetecting Bank%d\n", cs);
124 bank_size = get_ddr_bank_size(cs,
125 (volatile long*)(CFG_DDR_BASE + size));
128 debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
130 /* exit if less than one bank */
131 if(size < DDR_MAX_SIZE_PER_CS) break;
137 /**************************************************************************
140 int checkboard (void)
142 puts("Board: TQM834x\n");
145 DECLARE_GLOBAL_DATA_PTR;
146 volatile immap_t * immr;
149 immr = (immap_t *)CFG_IMMRBAR;
150 if (!(immr->reset.rcwh & RCWH_PCIHOST)) {
151 printf("PCI: NOT in host mode..?!\n");
157 if (immr->reset.rcwh & RCWH_PCI64)
163 printf("PCI1: %d bit, %d MHz\n", w, f / 1000000);
165 printf("PCI: disabled\n");
171 /**************************************************************************
175 *************************************************************************/
177 /**************************************************************************
178 * Detect the number of flash banks (1 or 2). Store it in
179 * a global variable tqm834x_num_flash_banks.
180 * Bank detection code based on the Monitor code.
182 static int detect_num_flash_banks(void)
184 typedef unsigned long FLASH_PORT_WIDTH;
185 typedef volatile unsigned long FLASH_PORT_WIDTHV;
194 tqm834x_num_flash_banks = 2; /* assume two banks */
196 /* Get bank 1 and 2 information */
197 bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
198 debug("Bank1 size: %lu\n", bank1_size);
199 bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1);
200 debug("Bank2 size: %lu\n", bank2_size);
201 total_size = bank1_size + bank2_size;
203 if (bank2_size > 0) {
204 /* Seems like we've got bank 2, but maybe it's mirrored 1 */
206 /* Set the base addresses */
207 bank1_base = (FPWV *) (CFG_FLASH_BASE);
208 bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size);
210 /* Put bank 2 into CFI command mode and read */
211 bank2_base[0x55] = 0x00980098;
214 bank2_read = bank2_base[0x10];
216 /* Read from bank 1 (it's in read mode) */
217 bank1_read = bank1_base[0x10];
220 bank1_base[0] = 0x00F000F0;
221 bank2_base[0] = 0x00F000F0;
223 if (bank2_read == bank1_read) {
225 * Looks like just one bank, but not sure yet. Let's
226 * read from bank 2 in autosoelect mode.
228 bank2_base[0x0555] = 0x00AA00AA;
229 bank2_base[0x02AA] = 0x00550055;
230 bank2_base[0x0555] = 0x00900090;
233 bank2_read = bank2_base[0x10];
235 /* Read from bank 1 (it's in read mode) */
236 bank1_read = bank1_base[0x10];
239 bank1_base[0] = 0x00F000F0;
240 bank2_base[0] = 0x00F000F0;
242 if (bank2_read == bank1_read) {
244 * In both CFI command and autoselect modes,
245 * we got the some data reading from Flash.
246 * There is only one mirrored bank.
248 tqm834x_num_flash_banks = 1;
249 total_size = bank1_size;
254 debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
256 /* set OR0 and BR0 */
257 im->lbus.bank[0].or = CFG_OR_TIMING_FLASH |
258 (-(total_size) & OR_GPCM_AM);
259 im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) |
260 (BR_MS_GPCM | BR_PS_32 | BR_V);
265 /*************************************************************************
266 * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
268 static long int get_ddr_bank_size(short cs, volatile long *base)
270 /* This array lists all valid DDR SDRAM configurations, with
271 * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
272 * The last entry has to to have size equal 0 and is igonred during
273 * autodection. Bank sizes must be in increasing order of size
280 {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20},
281 {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20},
282 {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20},
283 {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20},
284 {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20},
285 {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20},
286 {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20},
287 {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20},
296 for(i = 0; conf[i].size != 0; ++i) {
298 /* set sdram bank configuration */
299 set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
301 debug("Getting RAM size...\n");
302 size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
304 if((size == conf[i].size) && (i == detected + 1))
307 debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
316 /* disable empty cs */
317 debug("\nNo valid configurations for CS%d, disabling...\n", cs);
318 set_cs_config(cs, 0);
322 debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
323 conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
325 /* configure cs ro detected params */
326 set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
329 set_cs_bounds(cs, (long)base, conf[detected].size);
331 return(conf[detected].size);
334 /**************************************************************************
335 * Sets DDR bank CS bounds.
337 static void set_cs_bounds(short cs, long base, long size)
339 debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs);
341 im->ddr.csbnds[cs].csbnds = 0x00000000;
343 im->ddr.csbnds[cs].csbnds =
344 ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
345 (((base + size - 1) >> CSBNDS_EA_SHIFT) &
351 /**************************************************************************
352 * Sets DDR banks CS configuration.
353 * config == 0x00000000 disables the CS.
355 static void set_cs_config(short cs, long config)
357 debug("Setting config %08x for cs %d\n", config, cs);
358 im->ddr.cs_config[cs] = config;
362 /**************************************************************************
363 * Sets DDR clocks, timings and configuration.
365 static void set_ddr_config(void) {
367 im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
368 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
371 /* timing configuration */
372 im->ddr.timing_cfg_1 =
373 (4 << TIMING_CFG1_PRETOACT_SHIFT) |
374 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
375 (4 << TIMING_CFG1_ACTTORW_SHIFT) |
376 (5 << TIMING_CFG1_REFREC_SHIFT) |
377 (3 << TIMING_CFG1_WRREC_SHIFT) |
378 (3 << TIMING_CFG1_ACTTOACT_SHIFT) |
379 (1 << TIMING_CFG1_WRTORD_SHIFT) |
380 (TIMING_CFG1_CASLAT & TIMING_CASLAT);
382 im->ddr.timing_cfg_2 =
383 TIMING_CFG2_CPO_DEF |
384 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
387 /* don't enable DDR controller yet */
390 SDRAM_CFG_SDRAM_TYPE_DDR;
395 ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
396 SDRAM_MODE_ESD_SHIFT) |
397 ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
398 SDRAM_MODE_SD_SHIFT) |
399 ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
403 /* Set fast SDRAM refresh rate */
404 im->ddr.sdram_interval =
405 (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
406 (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);