1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
7 * Author: Markus Niebel <markus.niebel@tq-group.com>
9 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/arch/imx-regs.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/sys_proto.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
23 #include <asm/mach-imx/boot_mode.h>
24 #include <asm/mach-imx/mxc_i2c.h>
27 #include <fsl_esdhc_imx.h>
28 #include <linux/libfdt.h>
38 #define UART4_PAD_CTRL ( \
40 PAD_CTL_PUS_100K_UP | \
48 static iomux_v3_cfg_t const uart4_pads[] = {
49 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B, UART4_PAD_CTRL),
50 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B, UART4_PAD_CTRL),
51 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA, UART4_PAD_CTRL),
52 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA, UART4_PAD_CTRL),
55 static void setup_iomuxc_uart4(void)
57 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
61 #define USDHC2_PAD_CTRL ( \
63 PAD_CTL_PUS_47K_UP | \
69 #define USDHC2_CLK_PAD_CTRL ( \
71 PAD_CTL_PUS_47K_UP | \
77 static iomux_v3_cfg_t const usdhc2_pads[] = {
78 NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC2_CLK_PAD_CTRL),
79 NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL),
80 NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL),
81 NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL),
82 NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL),
83 NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL),
85 NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, USDHC2_PAD_CTRL), /* CD */
86 NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP, USDHC2_PAD_CTRL), /* WP */
89 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
90 #define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
92 static struct fsl_esdhc_cfg usdhc2_cfg = {
93 .esdhc_base = USDHC2_BASE_ADDR,
97 int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
99 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
102 if (cfg->esdhc_base == USDHC2_BASE_ADDR)
103 ret = !gpio_get_value(USDHC2_CD_GPIO);
108 int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
110 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
113 if (cfg->esdhc_base == USDHC2_BASE_ADDR)
114 ret = gpio_get_value(USDHC2_WP_GPIO);
119 int tqma6_bb_board_mmc_init(struct bd_info *bis)
123 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
125 ret = gpio_request(USDHC2_CD_GPIO, "mmc-cd");
127 gpio_direction_input(USDHC2_CD_GPIO);
128 ret = gpio_request(USDHC2_WP_GPIO, "mmc-wp");
130 gpio_direction_input(USDHC2_WP_GPIO);
132 usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
133 if(fsl_esdhc_initialize(bis, &usdhc2_cfg))
134 puts("WARNING: failed to initialize SD\n");
140 #define ENET_PAD_CTRL ( \
142 PAD_CTL_PUS_100K_UP | \
145 PAD_CTL_SPEED_MED | \
146 PAD_CTL_DSE_40ohm | \
150 static iomux_v3_cfg_t const enet_pads[] = {
151 NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
152 NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
153 NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL),
154 NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0, ENET_PAD_CTRL),
155 NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1, ENET_PAD_CTRL),
156 NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN, ENET_PAD_CTRL),
157 NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER, ENET_PAD_CTRL),
158 NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0, ENET_PAD_CTRL),
159 NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1, ENET_PAD_CTRL),
160 NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN, ENET_PAD_CTRL),
161 NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER, ENET_PAD_CTRL),
164 NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, ENET_PAD_CTRL),
165 /* ENET1 interrupt */
166 NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09, ENET_PAD_CTRL),
169 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8)
171 static void setup_iomuxc_enet(void)
175 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
177 /* Reset LAN8720 PHY */
178 ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
180 gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
182 gpio_set_value(ENET_PHY_RESET_GPIO, 1);
185 int board_eth_init(struct bd_info *bis)
187 return cpu_eth_init(bis);
191 #define GPIO_PAD_CTRL ( \
193 PAD_CTL_PUS_100K_UP | \
195 PAD_CTL_SPEED_MED | \
196 PAD_CTL_DSE_40ohm | \
200 #define GPIO_OD_PAD_CTRL ( \
202 PAD_CTL_PUS_100K_UP | \
205 PAD_CTL_SPEED_MED | \
206 PAD_CTL_DSE_40ohm | \
210 static iomux_v3_cfg_t const gpio_pads[] = {
212 NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00, GPIO_PAD_CTRL),
214 NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL),
216 NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07, GPIO_OD_PAD_CTRL),
218 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08, GPIO_PAD_CTRL),
220 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10, GPIO_PAD_CTRL),
222 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12, GPIO_PAD_CTRL),
225 #define GPIO_USB_H_PWR IMX_GPIO_NR(1, 0)
226 #define GPIO_USB_OTG_PWR IMX_GPIO_NR(3, 22)
227 #define GPIO_PCIE_RST IMX_GPIO_NR(6, 7)
228 #define GPIO_UART1_PWRON IMX_GPIO_NR(5, 8)
229 #define GPIO_UART2_PWRON IMX_GPIO_NR(5, 10)
230 #define GPIO_UART3_PWRON IMX_GPIO_NR(5, 12)
232 static void gpio_init(void)
236 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
238 ret = gpio_request(GPIO_USB_H_PWR, "usb-h-pwr");
240 gpio_direction_output(GPIO_USB_H_PWR, 1);
241 ret = gpio_request(GPIO_USB_OTG_PWR, "usb-otg-pwr");
243 gpio_direction_output(GPIO_USB_OTG_PWR, 1);
244 ret = gpio_request(GPIO_PCIE_RST, "pcie-reset");
246 gpio_direction_output(GPIO_PCIE_RST, 1);
247 ret = gpio_request(GPIO_UART1_PWRON, "uart1-pwr");
249 gpio_direction_output(GPIO_UART1_PWRON, 0);
250 ret = gpio_request(GPIO_UART2_PWRON, "uart2-pwr");
252 gpio_direction_output(GPIO_UART2_PWRON, 0);
253 ret = gpio_request(GPIO_UART3_PWRON, "uart3-pwr");
255 gpio_direction_output(GPIO_UART3_PWRON, 0);
258 void tqma6_iomuxc_spi(void)
260 /* No SPI on this baseboard */
263 int tqma6_bb_board_early_init_f(void)
265 setup_iomuxc_uart4();
270 int tqma6_bb_board_init(void)
276 /* Turn the UART-couplers on one-after-another */
277 gpio_set_value(GPIO_UART1_PWRON, 1);
279 gpio_set_value(GPIO_UART2_PWRON, 1);
281 gpio_set_value(GPIO_UART3_PWRON, 1);
286 int tqma6_bb_board_late_init(void)
291 const char *tqma6_bb_get_boardname(void)
296 static const struct boot_mode board_boot_modes[] = {
297 /* 4 bit bus width */
298 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
299 /* 8 bit bus width */
300 {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
304 int misc_init_r(void)
306 add_board_boot_modes(board_boot_modes);
311 #define WRU4_USB_H1_PWR IMX_GPIO_NR(1, 0)
312 #define WRU4_USB_OTG_PWR IMX_GPIO_NR(3, 22)
314 int board_ehci_hcd_init(int port)
318 ret = gpio_request(WRU4_USB_H1_PWR, "usb-h1-pwr");
320 gpio_direction_output(WRU4_USB_H1_PWR, 1);
322 ret = gpio_request(WRU4_USB_OTG_PWR, "usb-OTG-pwr");
324 gpio_direction_output(WRU4_USB_OTG_PWR, 1);
329 int board_ehci_power(int port, int on)
332 gpio_set_value(WRU4_USB_OTG_PWR, on);
334 gpio_set_value(WRU4_USB_H1_PWR, on);
340 * Device Tree Support
342 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
343 void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd)
347 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */