2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
6 * Author: Markus Niebel <markus.niebel@tq-group.com>
8 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/errno.h>
19 #include <asm/imx-common/mxc_i2c.h>
20 #include <asm/imx-common/spi.h>
22 #include <fsl_esdhc.h>
26 #include <power/pfuze100_pmic.h>
27 #include <power/pmic.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
34 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
37 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39 #define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
40 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
42 #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
43 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
45 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
46 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
48 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
49 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
50 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
54 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
59 static const uint16_t tqma6_emmc_dsr = 0x0100;
61 /* eMMC on USDHCI3 always present */
62 static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
63 NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
64 NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
65 NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
66 NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
67 NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
68 NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
69 NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
70 NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
71 NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
72 NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
74 NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
78 * According to board_mmc_init() the following map is done:
79 * (U-boot device node) (Physical Port)
80 * mmc0 eMMC (SD3) on TQMa6
81 * mmc1 .. n optional slots used on baseboard
83 struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
84 .esdhc_base = USDHC3_BASE_ADDR,
88 int board_mmc_getcd(struct mmc *mmc)
90 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
93 if (cfg->esdhc_base == USDHC3_BASE_ADDR)
94 /* eMMC/uSDHC3 is always present */
97 ret = tqma6_bb_board_mmc_getcd(mmc);
102 int board_mmc_getwp(struct mmc *mmc)
104 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
107 if (cfg->esdhc_base == USDHC3_BASE_ADDR)
108 /* eMMC/uSDHC3 is always present */
111 ret = tqma6_bb_board_mmc_getwp(mmc);
116 int board_mmc_init(bd_t *bis)
118 imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
119 ARRAY_SIZE(tqma6_usdhc3_pads));
120 tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
121 if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
122 puts("Warning: failed to initialize eMMC dev\n");
124 struct mmc *mmc = find_mmc_device(0);
126 mmc_set_dsr(mmc, tqma6_emmc_dsr);
129 tqma6_bb_board_mmc_init(bis);
134 static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
136 NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
137 NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
138 NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
139 NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
142 #define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
144 static unsigned const tqma6_ecspi1_cs[] = {
148 static void tqma6_iomuxc_spi(void)
152 for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
153 gpio_direction_output(tqma6_ecspi1_cs[i], 1);
154 imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
155 ARRAY_SIZE(tqma6_ecspi1_pads));
158 int board_spi_cs_gpio(unsigned bus, unsigned cs)
160 return ((bus == CONFIG_SF_DEFAULT_BUS) &&
161 (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
164 static struct i2c_pads_info tqma6_i2c3_pads = {
165 /* I2C3: on board LM75, M24C64, */
167 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
169 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
171 .gp = IMX_GPIO_NR(1, 5)
174 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
176 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
178 .gp = IMX_GPIO_NR(1, 6)
182 static void tqma6_setup_i2c(void)
184 /* use logical index for bus, e.g. I2C1 -> 0 */
185 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
188 int board_early_init_f(void)
190 return tqma6_bb_board_early_init_f();
195 /* address of boot parameters */
196 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
201 tqma6_bb_board_init();
206 static const char *tqma6_get_boardname(void)
208 u32 cpurev = get_cpu_rev();
210 switch ((cpurev & 0xFF000) >> 12) {
211 case MXC_CPU_MX6SOLO:
228 int board_late_init(void)
233 setenv("board_name", tqma6_get_boardname());
236 * configure PFUZE100 PMIC:
237 * TODO: should go to power_init_board if bus switching is
238 * fixed in generic power code
240 power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
241 p = pmic_get("PFUZE100");
242 if (p && !pmic_probe(p)) {
243 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
244 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
247 tqma6_bb_board_late_init();
254 printf("Board: %s on a %s\n", tqma6_get_boardname(),
255 tqma6_bb_get_boardname());
260 * Device Tree Support
262 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
263 void ft_board_setup(void *blob, bd_t *bd)
265 /* bring in eMMC dsr settings */
266 do_fixup_by_path_u32(blob,
267 "/soc/aips-bus@02100000/usdhc@02198000",
268 "dsr", tqma6_emmc_dsr, 2);
269 tqma6_bb_ft_board_setup(blob, bd);
271 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */