2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2006
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
36 #ifdef CONFIG_VIDEO_SM501
40 #if defined(CONFIG_MPC5200_DDR)
41 #include "mt46v16m16-75.h"
43 #include "mt48lc16m16a2-75.h"
46 #ifdef CONFIG_OF_LIBFDT
47 #include <fdt_support.h>
48 #endif /* CONFIG_OF_LIBFDT */
50 DECLARE_GLOBAL_DATA_PTR;
53 void ps2mult_early_init(void);
57 static void sdram_start (int hi_addr)
59 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
61 /* unlock mode register */
62 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
64 __asm__ volatile ("sync");
66 /* precharge all banks */
67 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
69 __asm__ volatile ("sync");
72 /* set mode register: extended mode */
73 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
74 __asm__ volatile ("sync");
76 /* set mode register: reset DLL */
77 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
78 __asm__ volatile ("sync");
81 /* precharge all banks */
82 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
84 __asm__ volatile ("sync");
87 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
89 __asm__ volatile ("sync");
91 /* set mode register */
92 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
93 __asm__ volatile ("sync");
95 /* normal operation */
96 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
97 __asm__ volatile ("sync");
102 * ATTENTION: Although partially referenced initdram does NOT make real use
103 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
104 * is something else than 0x00000000.
107 long int initdram (int board_type)
116 /* setup SDRAM chip selects */
117 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
118 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
119 __asm__ volatile ("sync");
121 /* setup config registers */
122 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
123 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
124 __asm__ volatile ("sync");
128 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
129 __asm__ volatile ("sync");
132 /* find RAM size using SDRAM CS0 only */
134 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
136 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
144 /* memory smaller than 1MB is impossible */
145 if (dramsize < (1 << 20)) {
149 /* set SDRAM CS0 size according to the amount of RAM found */
151 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
152 __builtin_ffs(dramsize >> 20) - 1;
154 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
157 /* let SDRAM CS1 start right after CS0 */
158 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
160 /* find RAM size using SDRAM CS1 only */
163 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
166 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
175 /* memory smaller than 1MB is impossible */
176 if (dramsize2 < (1 << 20)) {
180 /* set SDRAM CS1 size according to the amount of RAM found */
182 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
183 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
185 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
188 #else /* CFG_RAMBOOT */
190 /* retrieve size of memory connected to SDRAM CS0 */
191 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
192 if (dramsize >= 0x13) {
193 dramsize = (1 << (dramsize - 0x13)) << 20;
198 /* retrieve size of memory connected to SDRAM CS1 */
199 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
200 if (dramsize2 >= 0x13) {
201 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
205 #endif /* CFG_RAMBOOT */
208 * On MPC5200B we need to set the special configuration delay in the
209 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
210 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
212 * "The SDelay should be written to a value of 0x00000004. It is
213 * required to account for changes caused by normal wafer processing
218 if ((SVR_MJREV(svr) >= 2) &&
219 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
221 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
222 __asm__ volatile ("sync");
225 #if defined(CONFIG_TQM5200_B)
226 return dramsize + dramsize2;
229 #endif /* CONFIG_TQM5200_B */
232 int checkboard (void)
234 #if defined(CONFIG_AEVFIFO)
235 puts ("Board: AEVFIFO\n");
239 #if defined(CONFIG_TQM5200S)
240 # define MODULE_NAME "TQM5200S"
242 # define MODULE_NAME "TQM5200"
245 #if defined(CONFIG_STK52XX)
246 # define CARRIER_NAME "STK52xx"
247 #elif defined(CONFIG_TB5200)
248 # define CARRIER_NAME "TB5200"
249 #elif defined(CONFIG_CAM5200)
250 # define CARRIER_NAME "CAM5200"
251 #elif defined(CONFIG_FO300)
252 # define CARRIER_NAME "FO300"
257 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
258 " on a " CARRIER_NAME " carrier board\n");
266 void flash_preinit(void)
269 * Now, when we are in RAM, enable flash write
270 * access for detection process.
271 * Note that CS_BOOT cannot be cleared when
272 * executing in flash.
274 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
279 static struct pci_controller hose;
281 extern void pci_mpc5xxx_init(struct pci_controller *);
283 void pci_init_board(void)
285 pci_mpc5xxx_init(&hose);
289 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
291 #if defined (CONFIG_MINIFAP)
292 #define SM501_POWER_MODE0_GATE 0x00000040UL
293 #define SM501_POWER_MODE1_GATE 0x00000048UL
294 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
295 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
296 #define SM501_GPIO_DATA_HIGH 0x00010004UL
297 #define SM501_GPIO_51 0x00080000UL
298 #endif /* CONFIG MINIFAP */
300 void init_ide_reset (void)
302 debug ("init_ide_reset\n");
304 #if defined (CONFIG_MINIFAP)
305 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
307 /* enable GPIO control (in both power modes) */
308 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
309 POWER_MODE_GATE_GPIO_PWM_I2C;
310 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
311 POWER_MODE_GATE_GPIO_PWM_I2C;
312 /* configure GPIO51 as output */
313 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
316 /* Configure PSC1_4 as GPIO output for ATA reset */
317 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
318 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
320 /* by default the ATA reset is de-asserted */
321 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
325 void ide_set_reset (int idereset)
327 debug ("ide_reset(%d)\n", idereset);
329 #if defined (CONFIG_MINIFAP)
331 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
334 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
339 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
341 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
349 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
350 * is left open, no keypress is detected.
352 int post_hotkeys_pressed(void)
354 #ifdef CONFIG_STK52XX
355 struct mpc5xxx_gpio *gpio;
357 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
360 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
361 * CODEC or UART mode. Consumer IrDA should still be possible.
363 gpio->port_config &= ~(0x07000000);
364 gpio->port_config |= 0x03000000;
366 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
367 gpio->simple_gpioe |= 0x20000000;
369 /* Configure GPIO_IRDA_1 as input */
370 gpio->simple_ddr &= ~(0x20000000);
372 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
379 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
381 void post_word_store (ulong a)
383 volatile ulong *save_addr =
384 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
389 ulong post_word_load (void)
391 volatile ulong *save_addr =
392 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
396 #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
398 #ifdef CONFIG_BOARD_EARLY_INIT_R
399 int board_early_init_r (void)
402 extern int usb_cpu_init(void);
404 #ifdef CONFIG_PS2MULT
405 ps2mult_early_init();
406 #endif /* CONFIG_PS2MULT */
408 #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
409 /* Low level USB init, required for proper kernel operation */
418 int silent_boot (void)
420 vu_long timer3_status;
422 /* Configure GPT3 as GPIO input */
423 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
425 /* Read in TIMER_3 pin status */
426 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
428 #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
429 /* Force silent console mode if S1 switch
430 * is in closed position (TIMER_3 pin status is LOW). */
431 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
434 /* Force silent console mode if S1 switch
435 * is in open position (TIMER_3 pin status is HIGH). */
436 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
443 int board_early_init_f (void)
446 gd->flags |= GD_FLG_SILENT;
450 #endif /* CONFIG_FO300 */
452 int last_stage_init (void)
455 * auto scan for really existing devices and re-set chip select
462 * Check for SRAM and SRAM size
465 /* save original SRAM content */
466 save = *(volatile u16 *)CFG_CS2_START;
469 /* write test pattern to SRAM */
470 *(volatile u16 *)CFG_CS2_START = 0xA5A5;
471 __asm__ volatile ("sync");
473 * Put a different pattern on the data lines: otherwise they may float
474 * long enough to read back what we wrote.
476 tmp = *(volatile u16 *)CFG_FLASH_BASE;
478 puts ("!! possible error in SRAM detection\n");
480 if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
481 /* no SRAM at all, disable cs */
482 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
483 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
484 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
486 __asm__ volatile ("sync");
487 } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
488 /* make sure that we access a mirrored address */
489 *(volatile u16 *)CFG_CS2_START = 0x1111;
490 __asm__ volatile ("sync");
491 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
492 /* SRAM size = 512 kByte */
493 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
495 __asm__ volatile ("sync");
496 puts ("SRAM: 512 kB\n");
499 puts ("!! possible error in SRAM detection\n");
501 puts ("SRAM: 1 MB\n");
503 /* restore origianl SRAM content */
505 *(volatile u16 *)CFG_CS2_START = save;
506 __asm__ volatile ("sync");
509 #ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
511 * Check for Grafic Controller
514 /* save origianl FB content */
515 save = *(volatile u16 *)CFG_CS1_START;
518 /* write test pattern to FB memory */
519 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
520 __asm__ volatile ("sync");
522 * Put a different pattern on the data lines: otherwise they may float
523 * long enough to read back what we wrote.
525 tmp = *(volatile u16 *)CFG_FLASH_BASE;
527 puts ("!! possible error in grafic controller detection\n");
529 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
530 /* no grafic controller at all, disable cs */
531 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
532 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
533 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
535 __asm__ volatile ("sync");
537 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
539 /* restore origianl FB content */
541 *(volatile u16 *)CFG_CS1_START = save;
542 __asm__ volatile ("sync");
547 setenv("bootdelay", "0");
551 #endif /* !CONFIG_TQM5200S */
556 #ifdef CONFIG_VIDEO_SM501
559 #define DISPLAY_WIDTH 800
561 #define DISPLAY_WIDTH 640
563 #define DISPLAY_HEIGHT 480
565 #ifdef CONFIG_VIDEO_SM501_8BPP
566 #error CONFIG_VIDEO_SM501_8BPP not supported.
567 #endif /* CONFIG_VIDEO_SM501_8BPP */
569 #ifdef CONFIG_VIDEO_SM501_16BPP
570 #error CONFIG_VIDEO_SM501_16BPP not supported.
571 #endif /* CONFIG_VIDEO_SM501_16BPP */
572 #ifdef CONFIG_VIDEO_SM501_32BPP
573 static const SMI_REGS init_regs [] =
577 {0x00048, 0x00021807},
578 {0x0004C, 0x10090a01},
580 {0x00040, 0x00021807},
581 {0x00044, 0x10090a01},
583 {0x80200, 0x00010000},
585 {0x80208, 0x0A000A00},
586 {0x8020C, 0x02fa027f},
587 {0x80210, 0x004a028b},
588 {0x80214, 0x020c01df},
589 {0x80218, 0x000201e9},
590 {0x80200, 0x00013306},
591 #else /* panel + CRT */
594 {0x00048, 0x00021807},
595 {0x0004C, 0x301a0a01},
597 {0x00040, 0x00021807},
598 {0x00044, 0x091a0a01},
600 {0x80000, 0x0f013106},
601 {0x80004, 0xc428bb17},
602 {0x8000C, 0x00000000},
603 {0x80010, 0x0C800C80},
604 {0x80014, 0x03200000},
605 {0x80018, 0x01e00000},
606 {0x8001C, 0x00000000},
607 {0x80020, 0x01e00320},
608 {0x80024, 0x042a031f},
609 {0x80028, 0x0086034a},
610 {0x8002C, 0x020c01df},
611 {0x80030, 0x000201ea},
612 {0x80200, 0x00010000},
615 {0x00048, 0x00021807},
616 {0x0004C, 0x091a0a01},
618 {0x00040, 0x00021807},
619 {0x00044, 0x091a0a01},
621 {0x80000, 0x0f013106},
622 {0x80004, 0xc428bb17},
623 {0x8000C, 0x00000000},
624 {0x80010, 0x0a000a00},
625 {0x80014, 0x02800000},
626 {0x80018, 0x01e00000},
627 {0x8001C, 0x00000000},
628 {0x80020, 0x01e00280},
629 {0x80024, 0x02fa027f},
630 {0x80028, 0x004a028b},
631 {0x8002C, 0x020c01df},
632 {0x80030, 0x000201e9},
633 {0x80200, 0x00010000},
634 #endif /* #ifdef CONFIG_FO300 */
638 #endif /* CONFIG_VIDEO_SM501_32BPP */
640 #ifdef CONFIG_CONSOLE_EXTRA_INFO
642 * Return text to be printed besides the logo.
644 void video_get_info_str (int line_number, char *info)
646 if (line_number == 1) {
647 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
648 #if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300)
649 } else if (line_number == 2) {
650 #if defined (CONFIG_STK52XX)
651 strcpy (info, " on a STK52xx carrier board");
653 #if defined (CONFIG_TB5200)
654 strcpy (info, " on a TB5200 carrier board");
656 #if defined (CONFIG_FO300)
657 strcpy (info, " on a FO300 carrier board");
668 * Returns SM501 register base address. First thing called in the
669 * driver. Checks if SM501 is physically present.
671 unsigned int board_video_init (void)
677 * Check for Grafic Controller
680 /* save origianl FB content */
681 save = *(volatile u16 *)CFG_CS1_START;
684 /* write test pattern to FB memory */
685 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
686 __asm__ volatile ("sync");
688 * Put a different pattern on the data lines: otherwise they may float
689 * long enough to read back what we wrote.
691 tmp = *(volatile u16 *)CFG_FLASH_BASE;
693 puts ("!! possible error in grafic controller detection\n");
695 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
696 /* no grafic controller found */
700 ret = SM501_MMIO_BASE;
704 *(volatile u16 *)CFG_CS1_START = save;
705 __asm__ volatile ("sync");
711 * Returns SM501 framebuffer address
713 unsigned int board_video_get_fb (void)
715 return SM501_FB_BASE;
719 * Called after initializing the SM501 and before clearing the screen.
721 void board_validate_screen (unsigned int base)
726 * Return a pointer to the initialization sequence.
728 const SMI_REGS *board_get_regs (void)
733 int board_get_width (void)
735 return DISPLAY_WIDTH;
738 int board_get_height (void)
740 return DISPLAY_HEIGHT;
743 #endif /* CONFIG_VIDEO_SM501 */
745 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
746 void ft_board_setup(void *blob, bd_t *bd)
748 ft_cpu_setup(blob, bd);
749 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
751 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */